PI7C9X130DNDE Pericom Semiconductor, PI7C9X130DNDE Datasheet - Page 99

IC PCIE-PCIX BRIDGE 1PORT 256BGA

PI7C9X130DNDE

Manufacturer Part Number
PI7C9X130DNDE
Description
IC PCIE-PCIX BRIDGE 1PORT 256BGA
Manufacturer
Pericom Semiconductor
Datasheets

Specifications of PI7C9X130DNDE

Applications
PCI-to-PCI Bridge
Interface
SMBus (2-Wire/I²C)
Voltage - Supply
1.8V, 3.3V
Package / Case
256-PBGA
Mounting Type
Surface Mount
Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Operating Temperature (max)
85C
Package Type
BGA
Rad Hardened
No
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Part Number
Manufacturer
Quantity
Price
Part Number:
PI7C9X130DNDE
Manufacturer:
Pericom
Quantity:
135
Part Number:
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Manufacturer:
NSC
Quantity:
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PI7C9X130DNDE
Manufacturer:
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7.5.35
7.5.36
7.5.37
PERICOM SEMICONDUCTOR - Confidential
SECONDARY CSR IO BASE ADDRESS REGISTER – OFFSET 54h
UPSTREAM IO OR MEMORY 1 BASE ADDRESS REGISTER – OFFSET 58h
UPSTREAM MEMORY 2 BASE ADDRESS REGISTER – OFFSET 5Ch
Bit
0
7:1
31:8
Bit
0
2:1
3
5:4
31:6
Bit
0
2:1
3
13:4
Function
Space Indicator
Reserved
Base Address
Function
Space Indicator
Address Type
Prefetchable control
Reserved
Base Address
Function
Space Indicator
Address Type
Prefetchable control
Reserved
Type
Type
Type
RO/RW
RW/RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Page 99 of 165
Description
0: Memory space
1: IO space
Reset to 1
Reset to 0
This Base Address Register maps to PI7C9X130 secondary IO space. The
maximum size is 256 bytes.
Reset to 00000000h
Description
0: Memory space
1: IO space
Reset to 0
00: 32-bit address decode range
01: 64-bit address decode range
10 and 11: reserved
Reset to 00
0: Memory space is non-prefetchable
1: Memory space is prefetchable
Reset to 0
Reset to 0
The size and type of this Base Address Register are defined from Upstream IO
or Memory 1 Setup Register (Offset ECh), which can be initialized by
EEPROM (I2C) or SM Bus or Local Processor. Writing a zero to bit [31] of
the setup register to disable this register. The range of this register is from 4KB
to 2GB for memory space or from 64B to 256B for IO space.
uses upstream IO or Memory 1 Translated Base Register (Offset E8h) to
formulate direct address translation. If a bit in the setup register is set to one,
then the correspondent bit of this register will be changed to RW.
Reset to 00000h
Description
0: Memory space
1: IO space
Reset to 0
00: 32-bit address decode range
01, 10 and 11: reserved
Reset to 00
0: Memory space is non-prefetchable
1: Memory space is prefetchable
Reset to 0
Reset to 0
PCI EXPRESS TO PCI-X BRIDGE
Mar 2010 - Rev 2.0
PI7X9X110A
PI7C9X130

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