PI7C9X130DNDE Pericom Semiconductor, PI7C9X130DNDE Datasheet - Page 21

• Manufacturer Part Number: PI7C9X130DNDE
• Description: IC PCIE-PCIX BRIDGE 1PORT 256BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X130DNDE

• Applications: PCI-to-PCI Bridge
• Interface: SMBus (2-Wire/I²C)
• Voltage - Supply: 1.8V, 3.3V
• Package / Case: 256-PBGA
• Mounting Type: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.6 MISCELLANEOUS SIGNALS
PERICOM SEMICONDUCTOR - Confidential
TCK
TMS
TDO
TDI
TRST_L
GPIO [6:0]
SMBCLK / SCL
SMBDAT / SDA
PME_L
CLKRUN_L
PCIXCAP
PCIXUP
DEV64
SEL100
HSEN
HSSW
LOO
ENUM_L
NAME
NAME
ASSIGNMENT
L13
M16
M14
M15
L14
L15, R10, P10,
R7, T7, N8, P8
B5
A5
C5
C4
A4
B3
E15
E14
R3
T3
N6
P6
ASSIGNMENT
PIN
PIN
Page 21 of 165
TYPE
TYPE
B/IOD
OD
IU
IU
IU
IU
O
B
B
B
B
O
O
I
I
I
I
I
Test Clock: TCK is the test clock to synchronize the state information
and data on the PCI bus side of PI7C9X130 during boundary scan
operation.
Test Mode Select: TMS controls the state of the Test Access Port
(TAP) controller.
Test Data Output: TDO is the test data output and connects to the end
of the JTAG scan chain.
Test Data Input: TDI is the test data input and connects to the
beginning of the JTAG scan chain. It allows the test instructions and
data to be serially shifted into the PCI side of PI7C9X130.
Test Reset (Active LOW): TRST_L is the test reset to initialize the
Test Access Port (TAP) controller.
General Purpose I/O Data Pins: The 7 general-purpose signals are
programmable as either input-only or bi-directional signals by writing
the GPIO output enable control register in the configuration space. See
chapter 8 for more information.
SMBUS / EEPROM Clock Pin: When EEPROM (I2C) interface is
selected (TM1=0), this pin is an output of SCL clock and connected to
EEPROM clock input. When SMBUS interface is selected (TM1=1),
this pin is an input for the clock of SMBUS.
SMBUS / EEPROM Data Pin: Data Interface Pin to EERPOM or
SMBUS. When EEPROM (I2C) interface is selected (TM1=0), this
pin is a bi-directional signal. When SMBUS interface is selected
(TM1=1), this pin is an open drain signal.
Power Management Event Pin: Power Management Event Signal is
asserted to request a change in the device or link power state.
Clock Run Pin (Active LOW): The Clock Run signal, for mobile
environment, is asserted and de-asserted to indicate the status of the PCI
Clock.
PCI-X Capability Pin: PI7C9X130 can be forced to PCI mode if
PCIXCAP is tied to ground with a capacitor (0.1uF) in parallel. If
PCIXCAP is connected to ground through a capacitor (0.1uF),
PI7C9X130 will be in 133MHz PCI-X mode. If PCIXCAP is
connected to ground through a resistor (10K Ohm) with a capacitor
(0.1uF) in parallel, PI7C9X130 will be in 66MHz PCI-X mode.
PCIXCAP Pull-up driver: PI7C9X130 drives this pin for PCI-X mode
detection.
Control 64-bit bus width: PI7C9X130 operates with 64-bit bus when
DEV64=1. When DEV64=0, PI7C9X130 operates with 32-bit bus.
Select 100MHz frequency: When SEL100=1, PI7C9X130 expects to
run at 100MHz clock. When SEL100=0, PI7C9X130 expects to run at
133MHz..
Hot Swap Enable: PI7C9X130 supports hot swap when HSEN is set
to high. Tie LOW if hot swap function is not used.
Hot Swap Switch: PI7C9X130 detects HSSW input to monitor the
insertion or impending extraction of a board.
LED On/Off: PI7C9X130 drives LOO for LED illumination that signals
the operator to extract the board.
ENUM_L signal: PI7C9X130 drives ENUM_L to notify the system
host that either a board has been freshly inserted or is about to be
extracted.
PCI EXPRESS TO PCI-X BRIDGE
DESCRIPTION
DESCRIPTION
Mar 2010 - Rev 2.0
PI7C9X130