PI7C9X130DNDE Pericom Semiconductor, PI7C9X130DNDE Datasheet - Page 59

• Manufacturer Part Number: PI7C9X130DNDE
• Description: IC PCIE-PCIX BRIDGE 1PORT 256BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X130DNDE

• Applications: PCI-to-PCI Bridge
• Interface: SMBus (2-Wire/I²C)
• Voltage - Supply: 1.8V, 3.3V
• Package / Case: 256-PBGA
• Mounting Type: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.4.50 DOWNSTREAM SPLIT TRANSACTION REGISTER – OFFSET 8Ch
7.4.51 POWER MANAGEMENT ID REGISTER – OFFSET 90h
7.4.52 NEXT CAPABILITY POINTER REGISTER – OFFSET 90h
7.4.53 POWER MANAGEMENT CAPABILITY REGISTER – OFFSET 90h
PERICOM SEMICONDUCTOR - Confidential
Bit
15:0
31:16
Bit
7:0
Bit
15:8
Bit
18:16
19
20
21
Function
Downstream Split
Transaction
Capability
Downstream Split
Transaction
Commitment Limit
Function
Power Management
ID
Function
Next Pointer
Function
Version Number
PME Clock
Reserved
Device Specific
Initialization (DSI)
Type
Type
Type
Type
RW
RO
RO
RO
RO
RO
RO
RO
Page 59 of 165
Description
Downstream Split Transaction Capability specifies the size of the buffer (in the
unit of ADQs) to store split completions for memory read. It applies to the
requesters on the primary bus in addressing the completers on the secondary
bus. The 0010h value shows that the buffer has 16 ADQs or 2K bytes storage
Reset to 0010h
Downstream Split Transaction Commitment Limit indicates the cumulative
sequence size of the commitment limit in units of ADQs. This field can be
programmed to any value or equal to the content of the split capability field.
For example, if the limit is set to FFFFh, PI7C9X130 is allowed to forward all
split requests of any size regardless of the amount of buffer space available.
The split transaction commitment limit is set to 0010h that is the same value as
the split transaction capability.
Reset to 0010h
Description
Power Management ID Register
Reset to 01h
Description
Next pointer (point to Subsystem ID and Subsystem Vendor ID)
Reset to A8h
Description
Version number that complies with revision 2.0 of the PCI Power Management
Interface specification.
Reset to 010
PME clock is not required for PME_L generation
Reset to 0
Reset to 0
DSI – no special initialization of this function beyond the standard PCI
configuration header is required following transition to the D0 un-initialized
state
Reset to 0
PCI EXPRESS TO PCI-X BRIDGE
Mar 2010 - Rev 2.0
PI7C9X130