PI7C9X130DNDE Pericom Semiconductor, PI7C9X130DNDE Datasheet - Page 48

• Manufacturer Part Number: PI7C9X130DNDE
• Description: IC PCIE-PCIX BRIDGE 1PORT 256BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X130DNDE

• Applications: PCI-to-PCI Bridge
• Interface: SMBus (2-Wire/I²C)
• Voltage - Supply: 1.8V, 3.3V
• Package / Case: 256-PBGA
• Mounting Type: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.4.31 PCI DATA BUFFERING CONTROL REGISTER – OFFSET 40h
PERICOM SEMICONDUCTOR - Confidential
Bit
19
20
21
22
23
24
25
26
27
31:28
Bit
0
1
Function
VGA Enable
VGA 16-bit Decode
Master Abort Mode
Secondary Interface
Reset
Fast Back-to-Back
Enable
Primary Master
Timeout
Secondary Master
Timeout
Master Timeout
Status
Discard Timer
SERR_L Enable
Reserved
Function
Secondary Internal
Arbiter’s PARK
Function
Memory Read
Prefetching Dynamic
Control Disable
Type
Type
RWC
RW
RW
RW
RW
RW
RW
RW
RW
RW
RO
RO
Page 48 of 165
Description
0: Do not forward VGA compatible memory and I/O addresses from the
primary to secondary, unless they are enabled for forwarding by the defined I/O
and memory address ranges
1: Forward VGA compatible memory and I/O addresses from the primary and
secondary (if the I/O enable and memory enable bits are set), independent of
the ISA enable bit
0: Execute 10-bit address decodes on VGA I/O accesses
1: Execute 16-bit address decode on VGA I/O accesses
Reset to 0
0: Do not report master aborts (return FFFFFFFFh on reads and discards data
on write)
1: Report master abort by signaling target abort if possible or by the assertion
of SERR_L (if enabled).
Reset to 0
0: Do not force the assertion of RESET_L on secondary PCI bus for forward
bridge, or do not generate a hot reset on the PCIe link for reverse bridge
1: Force the assertion of RESET_L on secondary PCI bus for forward bridge,
or generate a hot reset on the PCIe link for reverse bridge
Reset to 0
Fast back-to-back not supported
Reset to 0
0: Primary discard timer counts 2
1: Primary discard timer counts 2
FORWARD BRIDGE –
Bit is RO and ignored by the PI7C9X130
Reset to 0
0: Secondary discard timer counts 2
1: Secondary discard timer counts 2
REVERSE BRIDGE –
Bit is RO and ignored by PI7C9X130
Reset to 0
Bit is set when the discard timer expires and a delayed completion is discarded
at the PCI interface for the forward or reverse bridge
Reset to 0
Bit is set to enable to generate ERR_NONFATAL or ERR_FATAL for forward
bridge, or assert P_SERR_L for reverse bridge as a result of the expiration of
the discard timer on the PCI interface.
Reset to 0
Reset to 0000
Description
0: Park to the last master
1: Park to PI7C9X130 secondary port
Reset to 0
0: Enable memory read prefetching dynamic control for PCI to PCIe read
1: Disable memory read prefetching dynamic control for PCI to PCIe read
Reset to 0
PCI EXPRESS TO PCI-X BRIDGE
15
10
PCI clock cycles
PCI clock cycles
15
10
PCI clock cycles
PCI clock cycles
Mar 2010 - Rev 2.0
PI7C9X130