PI7C9X130DNDE Pericom Semiconductor, PI7C9X130DNDE Datasheet - Page 94

• Manufacturer Part Number: PI7C9X130DNDE
• Description: IC PCIE-PCIX BRIDGE 1PORT 256BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X130DNDE

• Applications: PCI-to-PCI Bridge
• Interface: SMBus (2-Wire/I²C)
• Voltage - Supply: 1.8V, 3.3V
• Package / Case: 256-PBGA
• Mounting Type: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.5.27
PERICOM SEMICONDUCTOR - Confidential
SECONDARY STATUS REGISTER – OFFSET 44h
Bit
10
15:11
Bit
18:16
19
20
21
22
23
24
26:25
27
Function
Secondary Interrupt
Disable
Reserved
Function
Reserved
Secondary Interrupt
Status
Capability List
Capable
66MHz Capable
Reserved
Fast Back-to-Back
Capable
Master Data Parity
Error Detected
DEVSEL_L Timing
(medium decode)
Signaled Target
Abort
Type
Type
RO / RW
RWC
RWC
RO
RO
RO
RO
RO
RO
RO
RO
Page 94 of 165
Description
0: INTx interrupt messages can be generated
1: Prevent INTx messages to be generated and any asserted INTx interrupts
will be released.
Reset to 0
Reset to 00000
Description
Reset to 000
0: No INTx interrupt message request pending in PI7C9X130 secondary
1: INTx interrupt message request pending in PI7C9X130 secondary
Reset to 0
1: PI7C9X130 supports the capability list (offset 34h in the pointer to the data
structure)
Reset to 1
This bit applies to forward bridge only.
1: 66MHz capable
Reset to 0 when reverse bridge or 1 when forward bridge.
Reset to 0
This bit applies to forward bridge only.
1: Enable fast back-to-back transactions
Reset to 0 when reverse bridge or 1 when forward bridge with secondary bus in
PCI mode
Bit set if its Parity Error Enable bit is set and either of the conditions occurs on
the secondary:
REVERSE BRIDGE –


FORWARD BRIDGE –



Reset to 0
These bits apply to forward bridge only.
00: fast DEVSEL_L decoding
01: medium DEVSEL_L decoding
10: slow DEVSEL_L decoding
11: reserved
Reset to 00 when reverse bridge or 01 when forward bridge.
REVERSE BRIDGE –
This bit is set when PI7C9X130 completes a request using completer abort
status on the secondary
FORWARD BRIDGE –
This bit is set to indicate a target abort on the secondary
Reset to 0
Receives a completion marked poisoned
Poisons a write request
Detected parity error when receiving data or Split Response for read
Observes P_PERR_L asserted when sending data or receiving Split
Response for write
Receives a Split Completion Message indicating data parity error
occurred for non-posted write
PCI EXPRESS TO PCI-X BRIDGE
Mar 2010 - Rev 2.0
PI7C9X130