PI7C9X130DNDE Pericom Semiconductor, PI7C9X130DNDE Datasheet - Page 47

• Manufacturer Part Number: PI7C9X130DNDE
• Description: IC PCIE-PCIX BRIDGE 1PORT 256BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X130DNDE

• Applications: PCI-to-PCI Bridge
• Interface: SMBus (2-Wire/I²C)
• Voltage - Supply: 1.8V, 3.3V
• Package / Case: 256-PBGA
• Mounting Type: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.4.27 EXPANSION ROM BASE ADDRESS REGISTER – OFFSET 38h
7.4.28 INTERRUPT LINE REGISTER – OFFSET 3Ch
7.4.29 INTERRUPT PIN REGISTER – OFFSET 3Ch
7.4.30 BRIDGE CONTROL REGISTER – OFFSET 3Ch
PERICOM SEMICONDUCTOR - Confidential
Bit
31:0
Bit
7:0
Bit
15:8
Bit
16
17
18
Function
Expansion ROM
Base Address
Function
Interrupt Line
Function
Interrupt Pin
Function
Parity Error
Response Enable
SERR_L Enable
ISA Enable
Type
Type
Type
Type
RW
RW
RW
RW
RO
RO
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Description
Expansion ROM not supported.
Reset to 00000000h
Description
These bits apply to reverse bridge only.
For initialization code to program to tell which input of the interrupt controller
the PI7C9X130’s INTA_L in connected to.
Reset to 00000000
Description
These bits apply to reverse bridge only.
Designates interrupt pin INTA_L, is used
Reset to 00h when forward mode or 01h when reverse mode.
Description
0: Ignore parity errors on the secondary
1: Enable parity error detection on secondary
FORWARD BRIDGE –
Controls the response to uncorrectable address attribute and data errors on the
secondary
REVERSE BRIDGE –
Controls the setting of the master data parity error bit in response to a received
poisoned TLP from the secondary (PCIe link)
Reset to 0
0: Disable the forwarding of SERR_L to ERR_FATAL and
ERR_NONFATAL
1: Enable the forwarding of SERR_L to ERR_FATAL and
ERR_NONFATAL
Reset to 0 (FORWARD BRIDGE)
RO bit for REVERSE BRIDGE
0: Forward downstream all I/O addresses in the address range defined by the
I/O Base and Limit registers
1: Forward upstream all I/O addresses in the address range defined by the I/O
Base and Limit registers that are in the first 64KB of PCI I/O address space
(top 768 bytes of each 1KB block)
Reset to 0
PCI EXPRESS TO PCI-X BRIDGE
Mar 2010 - Rev 2.0
PI7C9X130