PEF82912FV1.4 Infineon Technologies, PEF82912FV1.4 Datasheet - Page 163

• Manufacturer Part Number: PEF82912FV1.4
• Description: ISDN Interface ISDN
• Manufacturer: Infineon Technologies

Specifications of PEF82912FV1.4

• Mounting Style: SMD/SMT
• Package / Case: MQFP-64
• Lead Free Status / Rohs Status: Details

CODR0
CIC0
CIC1
S/G
BAS
Note: The CODR0 bits are updated every time a new C/I-code is detected in two
Data Sheet
consecutive IOM-frames. If several consecutive valid new codes are detected and
CIR0 is not read, only the first and the last C/I code are made available in CIR0 at
the first and second read of that register.
C/I0 Code Receive
Value of the received Command/Indication code. A C/I-code is loaded in
CODR0 only after being the same in two consecutive IOM-frames and the
previous code has been read from CIR0.
C/I0 Code Change
0 = No change in the received Command/Indication code has been
1 = A change in the received Command/Indication code has been
C/I1 Code Change
0 = No change in the received Command/Indication code has been
1 = A change in the received Command/Indication code in IOM-channel 1
Stop/Go Bit Monitoring
Indicates the availability of the upstream D-channel;
0 = Go
1 = Stop
Bus Access Status
Indicates the state of the TIC-bus:
0 = the Q-SMINT I itself occupies the D- and C/I-channel
1 = another device occupies the D- and C/I-channel
recognized
recognized. This bit is set only when a new code is detected in two
consecutive IOM-frames. It is reset by a read of CIR0.
recognized
has been recognized. This bit is set when a new code is detected in
one IOM-frame. It is reset by a read of CIR0.
149
Register Description
PEF 82912/82913
2001-03-30