PEF82912FV1.4 Infineon Technologies, PEF82912FV1.4 Datasheet - Page 166

• Manufacturer Part Number: PEF82912FV1.4
• Description: ISDN Interface ISDN
• Manufacturer: Infineon Technologies

Specifications of PEF82912FV1.4

• Mounting Style: SMD/SMT
• Package / Case: MQFP-64
• Lead Free Status / Rohs Status: Details

CI1E
4.7
4.7.1
S_ CONF0
Value after reset: 40
DIS_TR
BUS
EN_ICV
Data Sheet
DIS_TR
7
Detailed S-Transceiver Registers
S_CONF0 - S-Transceiver Configuration Register 0
1 =
The C/I1 handler always reads and writes 6-bit values but if 4-bit is selected,
the higher two bits are ignored for interrupt generation. However, in write
direction the full CODX1 code is transmitted, i.e. the host must write the
higher two bits to “1”.
C/I1-channel Interrupt Enable
0 =
1 =
Disable Transceiver
0 =
1 =
Point-to-Point / Bus Selection
0 =
1 =
Enable Far End Code Violation
0 =
BUS
6 bit C/I1 channel width
Interrupt generation ISTA.CIC of CIR0.CIC1is masked
Interrupt generation ISTA.CIC of CIR0.CIC1 is enabled
All S-transceiver functions are enabled.
All S-transceiver functions are disabled and powered down (analog
and digital parts).
Adaptive Timing (Point-to-Point, extended passive bus).
Fixed Timing (Short passive bus), directly derived from transmit
clock.
normal operation.
H
EN_
ICV
0
read/write
152
L1SW
0
Register Description
PEF 82912/82913
EXLP
Address:
2001-03-30
0
0
30
H