PEF82912FV1.4 Infineon Technologies, PEF82912FV1.4 Datasheet - Page 198

• Manufacturer Part Number: PEF82912FV1.4
• Description: ISDN Interface ISDN
• Manufacturer: Infineon Technologies

Specifications of PEF82912FV1.4

• Mounting Style: SMD/SMT
• Package / Case: MQFP-64
• Lead Free Status / Rohs Status: Details

Bit 0..7
Bit 6
4.11.7
The Read M4 bit register contains the last received and verified M4 bit data.
M4R
Reset Value:
AIB
UOA
SCO
Data Sheet
AIB
7
M4R - M4 Read
0 =
1 =
Partial Activation Control External/Automatic,
function corresponds to the MON-8 commands PACE and PACA
0 =
1 =
Interruption (according to ANSI)
0 =
1 =
U Activation Only
0 =
1 =
Start-on-Command Only Bit
indicates whether the DLC network will deactivate the loop between calls
(defined in Bellcore TR-NWT000397)
0 =
BE
UOA
6
M4 bit is controlled by state machine/ external pins (PS1,2)
M4 bit is controlled by C
SAI bit is controlled and UOA bit is evaluated by state machine
SAI bit is controlled via the µC, UOA=1 is reported to the state
machine
H
indicates interruption
inactive
indicates that only U is activated
inactive
Start-on-Command-Only mode active,
in LULT mode the U-transceiver shall initiate the start-up procedure
only upon command from the network (‘AR’ primitive)
M46
5
M45
4
read
184
M44
3
SCO
2
Register Description
PEF 82912/82913
DEA
Address:
1
2001-03-30
ACT
0
69
H