PEF82912FV1.4 Infineon Technologies, PEF82912FV1.4 Datasheet - Page 25

• Manufacturer Part Number: PEF82912FV1.4
• Description: ISDN Interface ISDN
• Manufacturer: Infineon Technologies

Specifications of PEF82912FV1.4

• Mounting Style: SMD/SMT
• Package / Case: MQFP-64
• Lead Free Status / Rohs Status: Details

Table 2
Data Sheet
Pin
10
9
5
6
15
18
19
20
43
44
47
Pin Definitions and Functions (cont’d)
Symbol
WR
R/W
ALE
RST
RSTO
INT
MCLK
EAW
SX1
SX2
SR1
Type
I
I
I
I
OD
OD
O
I
O
O
I
Function
Write
Indicates a write access to the registers (Intel
bus mode).
Read/Write
A HIGH identifies a valid host access as a read
operation and a LOW identifies a valid host
access as a write operation (Motorola bus
mode).
Address Latch Enable
An address on the external address/data bus
(multiplexed bus type only) is latched with the
falling edge of ALE.
ALE also selects the microcontroller interface
type (multiplexed or non multiplexed).
Reset:
Low active reset input. Schmitt-Trigger input
with hysteresis of typical 360 mV. Tie to ’1’ if not
used.
Reset Output:
Low active reset output.
Interrupt Request:
INT becomes active if the Q-SMINT I requests
an interrupt.
Microcontroller Clock:
Clock output for the microcontroller
Tie to ‘1‘
External Awake:
A low level on EAW during power down
activates the clock generation of the Q-
SMINT I, i.e. the IOM -2 interface provides
FSC, DCL and BCL for read and write
access.
S-Bus Transmitter Output (positive)
S-Bus Transmitter Output (negative)
S-Bus Receiver Input
11
1)
PEF 82912/82913
2001-03-30
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