PEF82912FV1.4 Infineon Technologies, PEF82912FV1.4 Datasheet - Page 219

• Manufacturer Part Number: PEF82912FV1.4
• Description: ISDN Interface ISDN
• Manufacturer: Infineon Technologies

Specifications of PEF82912FV1.4

• Mounting Style: SMD/SMT
• Package / Case: MQFP-64
• Lead Free Status / Rohs Status: Details

•
Figure 85
Microprocessor Interface Timing
•
Parameter
ALE pulse width
Address setup time to ALE
Address hold time from ALE
Address latch setup time to WR, RD
Address setup time
Address hold time
ALE guard time
DS delay after R/W setup
RD pulse width
Data output delay from RD
Data hold from RD
Data float from RD
RD control interval
W pulse width
Data setup time to W x CS
Data hold time W x CS
W control interval
R/W hold from CS x DS inactive
1)
Data Sheet
A0 - A6
CS x DS
control interval: t
between two consecutive read accesses to one of the registers ISTAU, FEBE or NEBE, respectively, must be
longer than 330ns. This does not limit t
registers, as for instance: ISTAU -(t
Non-Multiplexed Address Timing
RI
' is minimal 70ns for all registers except ISTAU, FEBE and NEBE. However, the time
1)
RI
)- ISTA -(t
RI
of read sequences, which involve intermediate read access to other
RI
)- ISTAH -(t
205
t
AS
RI
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
AA
AL
LA
ALS
AS
AH
AD
DSD
RR
RD
DH
DF
RI
WW
DW
WD
WI
RWD
)- ISTAU.
Address
Electrical Characteristics
Limit Values
min.
20
10
10
10
10
10
10
10
80
0
70
60
10
10
70
10
t
PEF 82912/82913
AH
max.
80
25
2001-03-30
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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