S5920Q Applied Micro Circuits Corporation, S5920Q Datasheet - Page 106

• Manufacturer Part Number: S5920Q
• Manufacturer: Applied Micro Circuits Corporation

Specifications of S5920Q

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Package Type: PQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

S5920 – PCI Product: PCI Bus Protocol
Target Latency
The PCI specification requires that a selected target
relinquish the bus should an access to that target
require more than eight PCI clock periods (16 clocks
for the first data phase, 8 clocks for each subsequent
data phase). This prevents slow target devices from
potentially monopolizing the PCI bus and also allows
more accurate estimations for bus access latency.
Note that a special mode is available to the user which
will allow for this mechanism to be disabled, thus vio-
lating the PCI 2.1 Specification. If a value of 0 is
programmed into the serial nvRAM location 45h, bit 0,
target latency is ignored. In this case, the S5920 will
never issue a retry/disconnect in the event of a slow
Add-On device. This programmable bit is only pro-
vided for flexibility, and most users should leave this bit
set to 1.
nvRAM Location 45h, bit 0 = 0 : No disconnect for slow
Add-On device.
nvRAM Location 45h, bit 0 = 1 : PCI 2.1 compliant
Target Locking
It is possible for a PCI bus master to obtain exclusive
access to a target (“locking”) through use of the PCI
bus signal LOCK#. LOCK# is different from the other
PCI bus signals because its ownership may belong to
any bus master, even if it does not currently have own-
ership of the PCI bus. The ownership of LOCK#, if not
already claimed by another master, may be achieved
by the current PCI bus master on the clock period fol-
lowing the initial assertion of FRAME#. Figure 6
describes the signal relationship for establishing a
lock. The ownership of LOCK#, once established, per-
sists even while other bus masters control the bus.
Ownership can only be relinquished by the master
which originally established the lock.
PCI Bus Access Latency Components
AMCC Confidential and Proprietary
REQ#
Asserted
--Arbitration Latency-- --Bus Acquisition--
GNT#
Asserted
Bus Access Latency
Latency
FRAME#
Asserted
--Target Latency--
TRDY#
Asserted
Figure 50. Figure 5. Target-Initiated Retry
Figure 51. Figure 6. Engaging the LOCK# Signal
PCLK
FRAME#
TRDY#
DEVSEL#
IRDY#
STOP#
(T) Driven by Target
(I) Driven by Initiator
LOCK#
PCLK
FRAME#
AD[31:0]
IRDY#
TRDY#
DEVSEL#
(I) Driven by Initiator
(T) Driven by Target
LOCK MECHANISM
AVAILABLE
(I)
(I)
(T)
(T)
(T)
(I)
(I)
(I)
(T)
(T)
1
1
Address
Target Retry
Signaled
MECHANISM
UPON FIRST
AVAI LABLE
ACCESS
Revision 1.02 – April 12, 2007
LOCK
2
ESTABLISHED
2
LOCK
(T
)
3
3
Data
Initiator
BECOMES
+ FRAME# to return
Sequences IRDY#
TARGET
LOCKED
to IDLE state
Data Book
4
4
BUS
IDLE
MAINTAINED
5
DS1596
LOCK
5
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