S5920Q Applied Micro Circuits Corporation, S5920Q Datasheet - Page 136

• Manufacturer Part Number: S5920Q
• Manufacturer: Applied Micro Circuits Corporation

Specifications of S5920Q

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Package Type: PQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

S5920 – PCI Product: Pass-Thru Operation
On bus signals PTATN#, PTBURST#, PTNUM[1:0],
PTWR and PTBE[3:0] will update on the next ADCLK.
Clock 1: Pass-Thru signals PTATN#, PTBURST#,
PTNUM[1:0], PTWR and PTBE[3:0] are driven to indi-
cate what action is required by Add-On logic. These
status signals are valid only when PTATN# is active.
Add-On logic can decode status signals upon the
assertion of PTATN#.
PTATN# Asserted. Indicates Pass-Thru access is
pending.
PTBURST# Asserted. The access has multiple data
phases.
PTNUM[1:0] 0h. Indicates the access is to Pass-Thru
region 0.
PTWR Asserted. Indicates the access is a write.
PTBE[3:0]# 0h. Indicates valid bytes for the first data
transfer.
Clock 2: The Add-On sees that a burst-write is being
requested by the PCI, so starts by reading the corre-
sponding address via PTADR#. Note that all 32 bits of
Figure 69. PCI to Add-On Passive Write to an 8-bit
AMCC Confidential and Proprietary
PTATN#
PTBURST#
PTNUM[1:0]
PTWR
PTBE[3:0]#
SELECT#
ADR[6:2]
BE[3:0]#
RD#
DQ[7:0]
DQ[31:8]
PTADR#
PTRDY#
ADCLK
0
1
0h
2
ADD[31:8]
ADD[7:0]
Eh
3
Dh
1h
30h
4
Bh
3h
9Ah
5
7h
7h
D4h
2Ch
0h
6
the APTA are output on the DQ bus when PTADR# is
asserted. The Add-On must be capable of latching the
upper 24 bits (if needed). The Add-On begins reading
the APTD Register (asserting SELECT#, ADR[6:2],
and RD#). The Add-On logic sees that all bytes are
valid (PTBE# = 0h), so starts the read by asserting
BE0#, to indicate that BYTE0 of the APTD is to be
driven on DQ[7:0] during the next clock cycle.
Clock 3: The Add-On logic latches the Pass-Thru
address. RD# and BE0# are sampled by the S5920,
so BYTE0 of the APTD is driven on DQ[7:0] and
PTBE0# is deasserted. The Add-On asserts RD# and
BE1#, thus requesting that BYTE1 of the APTD be
driven on the DQ bus during the next cycle.
Clock 4: The Add-On logic latches BYTE0. RD# and
BE1# are sampled asserted by the S5920, so BYTE1
of the APTD is driven on DQ[7:0] and PTBE1# is deas-
serted. The Add-On device asserts RD# and BE2#,
thus requesting that BYTE2 of the APTD be driven on
the DQ bus during the next cycle.
7h
0h
08h
7
Bh
8h
AAh
8
Dh
Ch
BBh
9
Eh
Eh
CCh
Revision 1.02 – April 12, 2007
10
Fh
DDh
11
Data Book
12
DS1596
13
136