S5920Q Applied Micro Circuits Corporation, S5920Q Datasheet - Page 115

• Manufacturer Part Number: S5920Q
• Manufacturer: Applied Micro Circuits Corporation

Specifications of S5920Q

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Package Type: PQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

S5920 – PCI Product: Mailbox Overview
Mailbox Interrupts
Although polling status is useful in some cases, polling requires continuous actions by the processor. Mailbox inter-
rupt capabilities are provided to avoid much of the processor overhead required by continuously polling status bits.
The Add-On and PCI interface can each generate interrupts on the incoming mailbox condition and/or the outgoing
mailbox condition. These can be individual enabled/disabled. A specific byte in the incoming mailbox and outgoing
mailbox is identified to generate the interrupt(s). The tasks required to setup the mailbox interrupts are as follows:
Enabling PCI mailbox interrupts:
Enabling Add-On mailbox interrupts:
With either the Add-On or PCI interface, these two steps can be performed with a single access to the appropriate
register. They are shown separately here for clarity.
Once interrupts are enabled, the interrupt service routine must access the mailboxes and clear the interrupt
source. A particular application may not require all of the steps shown. For instance, a design may only use the
incoming mailbox interrupts and not require support for the outgoing mailbox interrupts. The interrupt service rou-
tine tasks are as follows:
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1. Enable PCI outgoing mailbox interrupts. A specific byte within the outgoing mailboxes is identified to assert
2. Enable PCI incoming mailbox interrupts. A specific byte within the incoming mailboxes is identified to assert
1. Enable Add-On outgoing mailbox interrupts. A specific byte within the outgoing mailboxes is identified to
2. Enable Add-On incoming mailbox interrupts. A specific byte within the incoming mailboxes is identified to
INTA# when read by the Add-On interface.
INTA# when written by the Add-On interface.
assert IRQ# when read by the PCI interface.
assert IRQ# when written by the PCI interface.
INTCSR
INTCSR
INTCSR
INTCSR
AINT
AINT
AINT
AINT
Bit 4
Bits 1:0
Bit 12
Bits 9:8
Bit 12
Bits 9:8
Bit 4
Bits 1:0
Enable outgoing mailbox interrupts
Identify mailbox byte to generate interrupt
Enable incoming mailbox interrupts
Identify mailbox byte to generate interrupt
Enable outgoing mailbox interrupts
Identify mailbox byte to generate interrupt
Enable incoming mailbox interrupts
Identify mailbox byte to generate interrupt
Revision 1.02 – April 12, 2007
Data Book
DS1596
115