S5920Q Applied Micro Circuits Corporation, S5920Q Datasheet - Page 97

• Manufacturer Part Number: S5920Q
• Manufacturer: Applied Micro Circuits Corporation

Specifications of S5920Q

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Package Type: PQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

S5920 – PCI Product: Initialization
could not use the busy bit to determine when to start a
new write, but would need to insert a delay (deter-
mined by the “shut down” time of the nvRAM, between
5-10 ms). Fortunately, the S5920 implements the
Acknowledge Polling scheme described above, which
will not take away the busy bit until the write is truly fin-
ished, and the external nvRAM is available for
accesses.
The following sequence is used to perform nvRAM
writes when accessing the RCR/ARCR in a byte-
wide fashion:
AMCC Confidential and Proprietary
1. Verify that busy bit, RCR(31), is not set by read-
2. Write to RCR(31:29) = “100”, the command to
3. Write to RCR(23:16) with the low address byte.
4. Write to RCR(31:29) = “101”, the command to
5. Write to RCR(23:16) with the high address byte.
6. Write to RCR(31:29) = “111”, the command to
7. Poll the busy bit until it is no longer set. Once
ing RCR(31). If set, hold off starting the read
sequence (repeat step 1 until this bit clears).
load the low address byte. This will assert the
internal signal LOAD_LOW_ADDR, which is used
to enable the loading of the low-address register
(NVRAM_LOW_ADDR).
Since signal LOAD_LOW_ADDR is asserted, the
d a t a w i l l b e w r i t t e n t o t h e r e g i s t e r
N V R A M _ L O W _ A D D R .
LOAD_LOW_ADDR is asserted, a write to
RCR(23:16) will continue to overwrite register
NVRAM_LOW_ADDR.
load the high address byte. This will assert the
internal signal LOAD_HIGH_ADDR, which is
used to enable the loading of the high-address
register (NVRAM_HIGH_ADDR).
Since signal LOAD_HIGH_ADDR is asserted, the
d a t a w i l l b e w r i t t e n t o t h e r e g i s t e r
NVRAM_HIGH_ADDR. Note that as the nvRAM
address is limited to 11-bits, only the 3-lsb’s of
this write data is actually used. As long as
LOAD_HIGH_ADDR is asserted, a write to
RCR(23:16) will continue to overwrite register
NVRAM_HIGH_ADDR.
start the nvRAM read operation. This will set the
busy bit, RCR(31). The nvRAM interface control-
ler will now initiate a read operation to the
external nvRAM.
c l e a r e d , t h e r e a d d a ta w i l l b e l o c a t e d i n
R C R ( 2 3 : 1 6 ) . I n a d d i t i o n , e v a l u a t e t h e
XFER_FAIL flag (bit 28) to determine whether the
transfer was successful or not. If XFER_FAIL is
asserted, this indicates that a transfer to the
nvRAM did not receive an ACKNOWLEDGE, and
A s
l o n g
a s
When performing a word/double-word RCR
access, you can combine the data and control in
the same command. The following is the sequence
for a write:
The following sequence is used for a read:
1. Verify that busy bit, RCR(31), is not set by read-
2. Write to RCR(31:29) = “100” and RCR(23:16)
3. Write to RCR(31:29) = “101” and RCR(23:16)
4. Write to RCR(31:29) = “110” and RCR(23:16)
5. Poll the busy bit until it is no longer set. Once
1. Verify that the busy bit, RCR(31), is not set by
2. Write to RCR(31:29) = “100” and RCR(23:16)
3. Write to RCR(31:29) = “101” and RCR(23:16)
4. Write to RCR(31:29) = “111”. This will set the
5. Poll the busy bit until it is no longer set. Once
the read data in RCR(32:16) may not be valid.
This flag remains set until the start of the next
read/write operation.
ing RCR(31). If set, hold off starting the write
sequence (repeat step 1 until the bit clears).
with the low address byte. This will directly load
NVRAM_LOW_ADDR with RCR(23:16).
with the high address byte. This will directly load
NVRAM_HIGH_ADDR with RCR(23:16).
with the write data. This will directly load the write
data register with RCR(23:16). This will also set
the busy bit, RCR(31). The nvRAM interface con-
troller will now initiate a write operation to the
external nvRAM.
cleared, it is now safe to perform another write/
read operation to the external nvRAM. In addi-
tion, evaluate the XFER_FAIL flag (bit 28) to
determine whether the transfer was successful or
not. If XFER_FAIL is asserted, this indicates that
a transfer to the nvRAM did not receive an
ACKNOWLEDGE. The write should not be con-
sidered successful. This flag remains set until the
start of the next read/write operation.
reading RCR(31). If set, hold off starting the read
sequence (repeat step 1 until the bit clears).
with the low address byte. This will directly load
NVRAM_LOW_ADDR with RCR(23:16).
with the high address byte. This will directly load
NVRAM_HIGH_ADDR with RCR(23:16).
busy bit, RCR(31). The nvRAM interface control-
ler will now initiate a read operation with the
external nvRAM.
c l e a r e d , t h e r e a d d a ta w i l l b e l o c a t e d i n
R C R ( 2 3 : 1 6 ) . I n a d d i t i o n , e v a l u a t e t h e
XFER_FAIL flag (bit 28) to determine whether the
Revision 1.02 – April 12, 2007
Data Book
DS1596
97