S5920Q Applied Micro Circuits Corporation, S5920Q Datasheet - Page 31

S5920Q

Manufacturer Part Number
S5920Q
Description
Manufacturer
Applied Micro Circuits Corporation
Datasheet

Specifications of S5920Q

Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Operating Temperature (max)
70C
Package Type
PQFP
Rad Hardened
No
Lead Free Status / Rohs Status
Not Compliant

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S5920 – PCI Product: Architectural Overview
To increase data throughput, the Pass-Thru channel
incorporates two 32-byte FIFOs. One FIFO is dedi-
cated to PCI read data while the other is dedicated to
PCI write data. Enabling the write FIFO allows the
S5920 to accept zero wait state bursts from the PCI
bus regardless of the Add-On bus application design
speed. Figure 4 illustrates the Pass-Thru block.
Enabling the read FIFO allows data to be optionally
prefetched from the Add-On Bus. This can greatly
improve performance of slow Add-On bus designs.
PCI read cycles can be performed with zero wait
Figure 5. Pass-Thru Block Diagram
AMCC Confidential and Proprietary
Decode
Control
PCI
32
32
32-Byte
FIFO
Pass-Thru Register
Endian
Conv.
Status/CTRL Register
states since data has been prefetched into the FIFO.
Either of the write/read FIFOs can be disabled or
enabled to tune system performance.
The Add-On bus can be operated in two different
modes: active or passive. The passive mode of opera-
tion mimics that of the S5933 Add-On bus operation.
The user design drives S5920 pins to read or write
data. In active mode, the Add-On bus is driven from an
S5920 internal state machine. This reduces compo-
nent count in cost-sensitive designs. Active mode also
incorporates programmable wait states from 0 to 7.
Endian
Pass-Thru Register
Conv.
32-Byte
FIFO
Revision 1.02 – April 12, 2007
32
Add-On
Decode
Control
32
Data Book
DS1596
31

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