DSP56301PW80B1 Freescale Semiconductor, DSP56301PW80B1 Datasheet - Page 112

• Manufacturer Part Number: DSP56301PW80B1
• Manufacturer: Freescale Semiconductor

Specifications of DSP56301PW80B1

• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 80MHz
• Mips: 80
• Device Input Clock Speed: 80MHz
• Ram Size: 24KB
• Program Memory Size: Not RequiredKB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: TQFP
• Lead Free Status / Rohs Status: Not Compliant

Power Consumption Benchmark
A-6
M_DSR EQU $FFFFC9; DSP STATUS REGISTER (DSR)
M_DPAR EQU $FFFFC8; DSP PCI ADDRESS REGISTER (DPAR)
M_DPMC EQU $FFFFC7; DSP PCI MASTER CONTROL REGISTER (DPMC)
M_DPCR EQU $FFFFC6; DSP PCI CONTROL REGISTER (DPCR)
M_DCTR EQU $FFFFC5 ; DSP CONTROL REGISTER (DCTR)
;
M_HCIE EQU 0
M_STIE EQU 1
M_SRIE EQU 2
M_HF35 EQU $38 ; Host Flags 5-3 Mask
M_HF3 EQU 3
M_HF4 EQU 4
M_HF5 EQU 5
M_HINT EQU 6
M_HDSM EQU 13 ; Host Data Strobe Mode
M_HRWP EQU 14 ; Host RD/WR Polarity
M_HTAP EQU 15 ; Host Transfer Acknowledge Polarity
M_HDRP EQU 16 ; Host Dma Request Polarity
M_HRSP EQU 17 ; Host Reset Polarity
M_HIRP EQU 18 ; Host Interrupt Request Polarity
M_HIRC EQU 19 ; Host Interupt Request Control
M_HM0 EQU 20
M_HM1 EQU 21
M_HM2 EQU 22
M_HM EQU $700000 ; Host Interface Mode Mask
;
M_PMTIE EQU 1 ; PCI Master Transmit Interrupt Enable
M_PMRIE EQU 2 ; PCI Master Receive Interrupt Enable
M_PMAIE EQU 4 ; PCI Master Address Interrupt Enable
M_PPEIE EQU 5 ; PCI Parity Error Interrupt Enable
M_PTAIE EQU 7 ; PCI Transaction Abort Interrupt Enable
M_PTTIE EQU 9 ; PCI Transaction Termination Interrupt Enable
M_PTCIE EQU 12
M_CLRT EQU 14 ; Clear Transmitter
M_MTT EQU 15
M_SERF EQU 16 ; HSERR~ Force
M_MACE EQU 18 ; Master Access Counter Enable
M_MWSD EQU 19 ; Master Wait States Disable
M_RBLE EQU 20 ; Receive Buffer Lock Enable
M_IAE EQU 21
;
M_ARH EQU $00ffff; DSP PCI Transaction Address (High)
M_BL EQU $3f0000; PCI Data Burst Length
M_FC EQU $c00000; Data Transfer Format Control
;
M_ARL EQU $00ffff; DSP PCI Transaction Address (Low)
M_C EQU $0f0000; PCI Bus Command
M_BE EQU $f00000; PCI Byte Enables
;
M_HCP EQU 0
Host Control Register Bit Flags
Host PCI Control Register Bit Flags
Host PCI Master Control Register Bit Flags
Host PCI Address Register Bit Flags
DSP Status Register Bit Flags
; Host Command Interrupt Enable
; Slave Transmit Interrupt Enable
; Slave Receive Interrupt Enable
; Host Flag 3
; Host Flag 4
; Host Flag 5
; Host Interrupt A
; Host Interface Mode
; Host Interface Mode
; Host Interface Mode
; Master Transfer Terminate
; Insert Address Enable
; Host Command pending
; PCI Transfer Complete Interrupt Enable
DSP56301 Technical Data, Rev. 10
Freescale Semiconductor