DSP56301PW80B1 Freescale Semiconductor, DSP56301PW80B1 Datasheet - Page 6

• Manufacturer Part Number: DSP56301PW80B1
• Manufacturer: Freescale Semiconductor

Specifications of DSP56301PW80B1

• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 80MHz
• Mips: 80
• Device Input Clock Speed: 80MHz
• Ram Size: 24KB
• Program Memory Size: Not RequiredKB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: TQFP
• Lead Free Status / Rohs Status: Not Compliant

Signals/Connections
1-2
PINIT/NMI
RAS[0–3]
CLKOUT
Notes:
AA[0–3]
GND
D[0-23]
A[0-23]
EXTAL
GND
GND
GND
GND
GND
GND
GND
PCAP
V
BCLK
BCLK
V
V
V
V
V
V
XTAL
CAS
CCQ
CCP
CCA
CCD
CCN
CCH
CCS
WR
RD
BR
BG
BS
BB
TA
BL
P1
Q
D
N
H
P
A
S
1.
2.
3.
4.
6
4
2
2
4
6
4
2
6
2
4
6
24
24
4
Power and ground connections are shown for the TQFP package. The MAP-BGA package uses one
V
BGA package uses two ground connections for the PLL (GND
connect to an internal ground plane.
The HI32 port supports PCI and non-PCI bus configurations. Twenty-four HI32 signals can also be
configured as GPIO signals (PB[0–23]).
The ESSI0, ESSI1, and SCI signals are multiplexed with the Port C GPIO signals (PC[0–5]), Port D
GPIO signals (PD[0–5]), and Port E GPIO signals (PE[0–2]), respectively.
TIO[0–2] can be configured as GPIO signals.
CCP
Power Inputs
PLL
Internal Logic
Address Bus
Data Bus
Bus Control
HI32
ESSI/SCI/Timer
Grounds
PLL
PLL
Internal Logic
Address Bus
Data Bus
Bus Control
HI32
ESSI/SCI/Timer
Port A
Clock
External
Address Bus
External
Data Bus
External
Bus
Control
PLL
for the PLL power input and 44 V
Figure 1-1.
1
:
DSP56301
1
:
DSP56301 Technical Data, Rev. 10
Extended Synchronous
Serial Interface Port 0
Interface (SCI) Port
Signals Identified by Functional Group
Synchronous Serial
Communications
Interface Port 1
(HI32) Port
JTAG/OnC
Extended
(ESSI0)
(ESSI1)
Interface
Interrupt
Timers
Control
CC
/Mode
E Port
Serial
Host
pins that connect to an internal power plane. The MAP-
2
3
3
3
4
3
52
3
TIO0
TIO1
TIO2
See Figure 1-2 for a listing of the
Host Interface/Port B Signals
MODA/IRQA
MODB/IRQB
MODC/IRQC
MODD/IRQD
RESET
PCI Bus
SC[00-02]
SCK0
SRD0
STD0
SC[10-12]
SCK1
SRD1
STD1
RXD
TXD
SCLK
TCK
TDI
TDO
TMS
TRST
DE
P
and GND
P1
Universal
Bus
) and 36 GND pins that
Port C GPIO
PC[0-2]
PC3
PC4
PC5
Port D GPIO
PD[0-2]
PD3
PD4
PD5
Port E GPIO
PE0
PE1
PE2
Timer GPIO
TIO0
TIO1
TIO2
Freescale Semiconductor
Port B
GPIO