DSP56301PW80B1 Freescale Semiconductor, DSP56301PW80B1 Datasheet - Page 114

• Manufacturer Part Number: DSP56301PW80B1
• Manufacturer: Freescale Semiconductor

Specifications of DSP56301PW80B1

• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 80MHz
• Mips: 80
• Device Input Clock Speed: 80MHz
• Ram Size: 24KB
• Program Memory Size: Not RequiredKB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: TQFP
• Lead Free Status / Rohs Status: Not Compliant

Power Consumption Benchmark
A-8
M_SCRE EQU 8
M_SCTE EQU 9
M_ILIE EQU 10
M_SCRIE EQU 11
M_SCTIE EQU 12
M_TMIE EQU 13
M_TIR EQU 14
M_SCKP EQU 15
M_REIE EQU 16
;
M_TRNE EQU 0
M_TDRE EQU 1
M_RDRF EQU 2
M_IDLE EQU 3
M_OR EQU 4
M_PE EQU 5
M_FE EQU 6
M_R8 EQU 7
;
M_CD EQU $FFF
M_COD EQU 12
M_SCP EQU 13
M_RCM EQU 14
M_TCM EQU 15
;------------------------------------------------------------------------
;
;
;
;------------------------------------------------------------------------
;
;
M_TX00 EQU $FFFFBC; SSI0 Transmit Data Register 0
M_TX01 EQU $FFFFBB; SSIO Transmit Data Register 1
M_TX02 EQU $FFFFBA; SSIO Transmit Data Register 2
M_TSR0 EQU $FFFFB9; SSI0 Time Slot Register
M_RX0 EQU $FFFFB8; SSI0 Receive Data Register
M_SSISR0 EQU $FFFFB7; SSI0 Status Register
M_CRB0 EQU $FFFFB6; SSI0 Control Register B
M_CRA0 EQU $FFFFB5; SSI0 Control Register A
M_TSMA0 EQU $FFFFB4; SSI0 Transmit Slot Mask Register A
M_TSMB0 EQU $FFFFB3; SSI0 Transmit Slot Mask Register B
M_RSMA0 EQU $FFFFB2; SSI0 Receive Slot Mask Register A
M_RSMB0 EQU $FFFFB1; SSI0 Receive Slot Mask Register B
;
M_TX10 EQU $FFFFAC; SSI1 Transmit Data Register 0
M_TX11 EQU $FFFFAB; SSI1 Transmit Data Register 1
M_TX12 EQU $FFFFAA; SSI1 Transmit Data Register 2
M_TSR1 EQU $FFFFA9; SSI1 Time Slot Register
M_RX1 EQU $FFFFA8; SSI1 Receive Data Register
M_SSISR1 EQU $FFFFA7; SSI1 Status Register
M_CRB1 EQU $FFFFA6; SSI1 Control Register B
M_CRA1 EQU $FFFFA5; SSI1 Control Register A
M_TSMA1 EQU $FFFFA4; SSI1 Transmit Slot Mask Register A
EQUATES for Synchronous Serial Interface (SSI)
SCI Status Register Bit Flags
SCI Clock Control Register
Register Addresses Of SSI0
Register Addresses Of SSI1
; Overrun Error Flag
; Parity Error
; Framing Error Flag
; Received Bit 8 (R8) Address
; Clock Divider Mask (CD0-CD11)
; Timer Interrupt Rate
; Clock Out Divider
; Clock Prescaler
; Receive Clock Mode Source Bit
; Transmit Clock Source Bit
; SCI Receiver Enable
; SCI Transmitter Enable
; Idle Line Interrupt Enable
; Timer Interrupt Enable
; SCI Clock Polarity
; SCI Error Interrupt Enable (REIE)
; Transmitter Empty
; Transmit Data Register Empty
; Receive Data Register Full
; Idle Line Flag
; SCI Receive Interrupt Enable
; SCI Transmit Interrupt Enable
DSP56301 Technical Data, Rev. 10
Freescale Semiconductor