DSP56301PW80B1 Freescale Semiconductor, DSP56301PW80B1 Datasheet - Page 30

• Manufacturer Part Number: DSP56301PW80B1
• Manufacturer: Freescale Semiconductor

Specifications of DSP56301PW80B1

• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 80MHz
• Mips: 80
• Device Input Clock Speed: 80MHz
• Ram Size: 24KB
• Program Memory Size: Not RequiredKB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: TQFP
• Lead Free Status / Rohs Status: Not Compliant

Specifications
2.5 AC Electrical Characteristics
The timing waveforms shown in the AC electrical characteristics section are tested with a V
and a V
Table 2-3. AC timing specifications, which are referenced to a device input signal, are measured in production with
respect to the 50 percent point of the respective input signal’s transition.
Note: Although the minimum value for the frequency of EXTAL is 0 MHz, the device AC test conditions are 15
2.5.1
2-4
Internal operation frequency and CLKOUT with PLL enabled
Internal operation frequency and CLKOUT with PLL disabled
Internal clock and CLKOUT high period
•
•
•
Internal clock and CLKOUT low period
•
•
•
Internal clock and CLKOUT cycle time with PLL enabled
Internal clock and CLKOUT cycle time with PLL disabled
Instruction cycle time
Notes:
With PLL disabled
With PLL enabled and MF ≤ 4
With PLL enabled and MF > 4
With PLL disabled
With PLL enabled and MF ≤ 4
With PLL enabled and MF > 4
IH
MHz and rated speed.
All specifications for the high impedance state are guaranteed by design.
1.
2.
minimum of 2.4 V for all pins except EXTAL, which is tested using the input levels shown in Note 6 of
Internal Clocks
DF = Division Factor; Ef = External frequency; ET
MF = Multiplication Factor; PDF = Predivision Factor; T
See the PLL and Clock Generator section in the DSP56300 Family Manual for details on the PLL.
Characteristics
Table 2-4.
DSP56301 Technical Data, Rev. 10
Internal Clocks, CLKOUT
C
= External clock cycle = 1/Ef;
C
I
CYC
= Internal clock cycle
Symbol
T
T
T
T
f
f
H
C
C
L
—
PDF × DF/MF
PDF × DF/MF
PDF × DF/MF
PDF × DF/MF
0.49 × ET
0.47 × ET
0.49 × ET
0.47 × ET
Min
—
—
—
—
—
—
C
C
C
C
×
×
×
×
Expression
T
C
(PDF × DF)
(Ef × MF)/
2 × ET
DF/MF
PDF ×
ET
Typ
Ef/2
ET
ET
—
—
—
—
Freescale Semiconductor
C
IL
C
C
×
C
maximum of 0.3 V
1, 2
—
PDF × DF/MF
PDF × DF/MF
PDF × DF/MF
PDF × DF/MF
0.51 × ET
0.53 × ET
0.51 × ET
0.53 × ET
Max
—
—
—
—
—
—
C
C
C
C
×
×
×
×