TXC-04222-AIOG Transwitch Corporation, TXC-04222-AIOG Datasheet - Page 12

• Manufacturer Part Number: TXC-04222-AIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-04222-AIOG

• Screening Level: Industrial
• Package Type: BGA
• Lead Free Status / Rohs Status: Not Compliant

June 2003
TEMx28
TXC-04222
TXC-04222-MB, Ed. 6
For a NRZ or positive/negative rail transmit interface, the line signal is written into two FIFOs, one for add A
side and the other for the B side, in one of the two Stuff/Synchronizer block pairs. Threshold modulation is used
for the frequency justification process. Timing information from the A and B drop buses or from the A and B add
buses is used to read the FIFO and perform the TU/VT justification process. The Synchronizer block permits
tracking of an incoming signal having an average frequency offset as high as 120 ppm, and up to 1.5 UI of
peak-to-peak jitter. Since the TEMx28 supports two different network architectures (DS1 and E1), two sets of
blocks are provided for each channel. The TU/VT A and B add bus selection can be different. The VT/TU add
bus selection can be different from the drop VT/TU selection. A control bit, and transmit line alarms, can also
generate DS1/E1 AIS.
The TU/VT Build blocks format the TU/VT into an STS-3 or STM-1 structure for the asynchronous DS1 or E1
signals. The pointer value carried in the V1 and V2 bytes is transmitted with a fixed value of 78 for the
VT1.5/TU-11 and 105 for the VT2/TU-12. Transmit access is provided for the eight overhead communications
channel bits (O-bits) via the microprocessor. The microprocessor also writes the signal label, and the value of
the J2 message, either as a 16-byte or a 64-byte message. The TEMx28 provides the TU tandem connection
feature for the TU-11 or TU-12, including the transmission of the 16-byte message and the various alarms
associated with the tandem connection feature. The device provides either single-bit or three-bit RDI using the
V5 and K4 bytes. Local alarms, or the microprocessor, can generate the remote payload, server, or connectivity
defect indications. The Remote Error Indication (REI) is inserted from the BIP-2 errors detected on the receive
side, and BIP-2 parity is generated for the V5 byte. Control bits are provided for generating unequipped status,
generating TU/VT AIS, and inserting REI and BIP-2 errors in the V5 byte. Control bits are also provided that
enable the microprocessor to insert overhead byte test values, including the V1/V2 pointer bytes and the V4
byte.
The A Transmit block is identical to the B Transmit block. The interface between an add bus and a Transmit
block consists of three input leads and ten output leads, when the add bus timing mode is selected. The input
leads are a byte clock, a C1J1V1 indicator, and an SPE indicator. The output leads are byte-wide data, and a
parity indicator, and an add-to-bus indicator signal. The Add C1J1V1 signal is used in conjunction with the Add
SPE signal to determine the location of the various bytes in the SONET/SDH format.
When drop bus timing is selected, the output leads are byte-wide data, a parity indicator, and an add-to-bus
indicator. The add bus clock, SPE and C1J1V1 signals, which are derived from the drop bus, can disabled or
provided. The selection is performed by a lead.
The Microprocessor Input/Output Interface block consists of an Intel- or Motorola-compatible split address/data
bus interface that provides access to assigned TEMx28 memory map addresses. Interrupt capability, interrupt
mask bits, alarm summary bits, and software polling bits are also provided. The alarms that cause the interrupt
can be set on positive, negative, or both positive and negative transitions.
Control bits are provided which enable a facility or a line loopback. In addition, a PRBS analyzer and generator
are provided. A 2
or add line direction for additional testing flexibility.
The Test Access Port (TAP) block provides a five-lead Boundary Scan capability that conforms to the IEEE
1149.1 standard. This standard provides external boundary scan functions to read and write the external
Input/Output leads from the TAP for board and component test.
The TEMx28 software driver has the same architecture of the other TranSwitch device drivers such as the
ML3M software, and is meant to be easily integrated with them. The application software calls the driver
functions to configure, control and manage the TEMx28 device. The device driver insulates the application from
the internal details of the device register usage and provides a higher level of abstraction. Particularly powerful
are the default configurations provided within the driver that allow one single command to bring the device to
operational mode.
15
Proprietary TranSwitch Corporation Information for use Solely by its Customers
-1 or 2
20
-1 PRBS pattern is supported. The analyzer and generator can be used in the drop
DATA SHEET
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