TXC-04222-AIOG Transwitch Corporation, TXC-04222-AIOG Datasheet - Page 54

• Manufacturer Part Number: TXC-04222-AIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-04222-AIOG

• Screening Level: Industrial
• Package Type: BGA
• Lead Free Status / Rohs Status: Not Compliant

June 2003
TEMx28
TXC-04222
TXC-04222-MB, Ed. 6
BUS TIMING
Timing for adding a TU/VT to the add bus is derived from the like-named drop bus, or from the like-named add
bus. The add bus timing-source selection is determined by lead ABUST, as shown in the table below. For the
drop bus timing mode, the add bus timing is derived from the drop bus clock, C1J1(V1), and SPE signals. The
V1 pulse may be present in the C1J signal or may be derived from internal H4 multiframe detectors. An option
is also provided in which the internal clock, C1J1V1, and SPE signals may be provided as outputs on the A and
B Add buses in the drop bus timing mode. For Add bus timing, an input clock, C1J1V1, and SPE signal must
be provided as input signals.
PERFORMANCE COUNTERS
There are three types of performance counters provided: saturating/rollover, current one second, and previous
one-second counters.
All counters, other than the one-second counters, can be configured as saturating (when control bit CROV (bit
0, 01AH) is a 0), or rollover (when control bit CROV is a 1). When a counter is configured to be saturating, it
stops at its maximum count. A rollover counter rolls over to zero after maximum count is reached.
A saturating counter is reset to 0 by a hardware reset (RESET lead), the software reset (RESETH control bit),
when it is read by the microprocessor, or by any of the following resets as they apply: RESETC (resets all per-
formance counters), DRESET (resets all drop side performance counters), DACHnR/DBCHnR (resets all A/B
drop side performance counters for a selected channel), TRESET (resets all add side performance counters),
and TnRESET (resets all add side performance counters for a selected channel).
A rollover counter is reset to FFFEH/FEH by a software reset. A hardware reset sets the CROV bit to 0 (satu-
rating) and all performance counters to 0. Rollover counters do not reset when read by the microprocessor.
The software resets must be held high for a minimum of one DSCLK clock cycle (excluding RESETH which is
self clearing). Since these resets are not self-clearing they must be brought low before another reset operation
can take place.
Reset action of the Current one-second and previous one-second counters is not dependent upon the CROV
control bit. These counters always reset to 0 (never FFFEH/FEH) by a hardware or software reset. For a 16-bit
counter, the low order byte must be read first, followed by a read of the high order byte, before any other low
order byte is read. During a microprocessor read cycle of any performance counter, counts are held and
updated afterwards to ensure that no counts are lost.
ALARM STRUCTURE
All alarm indications are reported as unlatched and latched status bits. The latched bit of an alarm can be set
on the positive transitions, negative transitions, or both positive and negative transitions. Reading a latched
alarm bit clears the bit to 0. Control bits INTR1 and INTR0 (bits 7 and 6, 01BH) should be programmed to
select the transition(s) on which the latched bits are set (see table below).
(bit 7, 01BH)
INTR1
0
1
0
1
Proprietary TranSwitch Corporation Information for use Solely by its Customers
ABUST lead
(bit 6, 01BH)
INTR0
High
Low
0
0
1
1
Not used. No latched alarm event indication, or interrupt indication.
Alarm sets latched alarm on positive transitions of the alarm.
Alarm sets latched alarm on negative transitions of the alarm.
Alarm sets latched alarm on positive or negative transitions of the alarm.
Add bus timing selected.
Drop bus timing selected.
DATA SHEET
Bus Timing Selection
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Action
Action on an Alarm