TXC-04222-AIOG Transwitch Corporation, TXC-04222-AIOG Datasheet - Page 99

• Manufacturer Part Number: TXC-04222-AIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-04222-AIOG

• Screening Level: Industrial
• Package Type: BGA
• Lead Free Status / Rohs Status: Not Compliant

BOUNDARY SCAN
Introduction
The Boundary Scan Interface Block provides a five-lead Test Access Port (TAP) that conforms to the IEEE
1149.1 standard. This standard provides external boundary scan functions to read and write the external
Input/Output leads from the TAP for board and component test.
The IEEE 1149.1 standard defines the requirements of a boundary scan architecture that has been specified
by the IEEE Joint Test Action Group (JTAG). Boundary scan is a specialized scan architecture that provides
observability and controllability for the interface leads of the device. As shown in Figure 41, one cell of a
boundary scan register is assigned to each input or output lead to be observed or tested (bidirectional leads
may have two cells). The boundary scan capability is based on a Test Access Port (TAP) controller, instruction
and bypass registers, and a boundary scan register bordering the input and output leads. The boundary scan
test bus interface consists of four input signals (Test Clock (TCK), Test Mode Select (TMS), Test Data Input
(TDI) and Test Reset (TRS)) and a Test Data Output (TDO) output signal. Boundary scan signal timing is
shown in Figure 25.
The TAP controller receives external control information via a Test Clock (TCK) signal and a Test Mode Select
(TMS) signal, and sends control signals to the internal scan paths. Detailed information on the operation of this
state machine can be found in the IEEE 1149.1 standard. The serial scan path architecture consists of an
instruction register, a boundary scan register and a bypass register. These three serial registers are connected
in parallel between the Test Data Input (TDI) and Test Data Output (TDO) signals, as shown in Figure 41.
The boundary scan function can be reset and disabled by holding lead TRS low. When boundary scan testing
is not being performed the boundary scan register is transparent, allowing the input and output signals to pass
to and from the TEMx28 device’s internal logic. During boundary scan testing, the boundary scan register may
disable the normal flow of input and output signals to allow the device to be controlled and observed via scan
operations.
Boundary Scan Operation
The maximum frequency the TEMx28 device will support for boundary scan is 10 MHz. The timing diagrams
for the boundary scan interface leads are shown in Figure 25.
The instruction register contains three bits. The TEMx28 device performs the following three boundary scan
test instructions:
Boundary Scan Reset
Specific control of the TRS lead is required in order to ensure that the boundary scan logic does not interfere
with normal device operation. This lead must either be held low, asserted low, or asserted low then high
(pulsed low), to asynchronously reset the Test Access Port (TAP) controller during power-up of the TEMx28. If
boundary scan testing is to be performed and the lead is held low, then a pull-down resistor value should be
chosen which will allow the tester to drive this lead high, but still meet the V
Output and Input/Output Parameters’ section of this Data Sheet for worst case leakage currents of all devices
sharing this pull-down resistor.
The EXTEST test instruction (000) provides the ability to test the connectivity of the TEMx28
device to external circuitry.
The SAMPLE test instruction (010) provides the ability to examine the boundary scan register
contents without interfering with device operation.
The BYPASS test instruction (111) provides the ability to bypass the TEMx28 boundary scan
and instruction registers.
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
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IL
requirements listed in the ‘Input,
TXC-04222-MB, Ed. 6
TXC-04222
TEMx28
June 2003