TXC-04222-AIOG Transwitch Corporation, TXC-04222-AIOG Datasheet - Page 3

• Manufacturer Part Number: TXC-04222-AIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-04222-AIOG

• Screening Level: Industrial
• Package Type: BGA
• Lead Free Status / Rohs Status: Not Compliant

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TEMx28 TXC-04222 Block Diagram ....................................................................................... 9
1544 kbit/s Asynchronous Mapping ....................................................................................... 13
2048 kbit/s Asynchronous Mapping ....................................................................................... 14
VC-11 to VC-12 Cross Mapping ............................................................................................ 15
Application Using the TEMx28 TXC-04222 ........................................................................... 16
TEMx28 TXC-04222 376-Lead Plastic Ball Grid Array Package Lead Diagram ................... 17
Channels 1 - 28 DS1/E1 Transmit Rail Interface Timing ....................................................... 32
Channels 1 - 28 DS1/E1 Transmit NRZ Interface Timing ...................................................... 33
Channels 1 - 28 Transmit VT/TU Interface Timing -Gapped Pointer Bytes ........................... 34
Channels 1 - 28 Transmit VT/TU Interface Timing-Gapped Pointer & POH Byte ................. 35
Channels 1 - 28 DS1/E1 Receive Rail Timing ....................................................................... 36
Channels 1 - 28 DS1/E1 Receive NRZ Timing ...................................................................... 37
Channels 1 - 28 Receive VT/TU Interface Timing -Gapped Pointer Bytes ............................ 38
Channels 1 - 28 Receive VT/TU Interface Timing-Gapped Pointer & POH Byte .................. 39
STS-3 A/B Drop and Add Bus Signals, Timing Derived from Drop Bus (lead ABTE low) ..... 40
STS-3 A/B Drop and Add Bus Signals, Timing Derived from Drop Bus (lead ABTE high) .... 41
STM-1 VC-4 A/B Drop and Add Bus Signals,
Timing Derived from Drop Bus (lead ABTE low) ................................................................... 42
STM-1 VC-4 A/B Drop and Add Bus Signals,
Timing Derived from Drop Bus (lead ABTE high) .................................................................. 43
STS-3 A/B Add Bus Signals, Timing Derived from Add Bus ................................................. 44
STM-1 VC-4 A/B Add Bus Signals, Timing Derived from Add Bus ....................................... 45
Microprocessor Read Cycle Timing - Intel ............................................................................. 46
Microprocessor Write Cycle Timing - Intel ............................................................................. 47
Microprocessor Read Cycle Timing - Motorola ..................................................................... 48
Microprocessor Write Cycle Timing - Motorola ..................................................................... 49
Boundary Scan Timing .......................................................................................................... 50
Alarm Latching Configurations .............................................................................................. 55
One Second (Shadow) Register Operation ........................................................................... 56
Channel Polling Alarms ......................................................................................................... 57
Global Indication Alarms ........................................................................................................ 58
Hardware Interrupt Indication ................................................................................................ 59
H4 Byte Floating VT Mode Bit Allocation ............................................................................... 61
VT/TU Pointer Tracking State Machine ................................................................................. 64
Loopback, Line AIS and PRBS Generator/Analyzer ............................................................. 87
E1 (2048 kbit/s) Jitter Tolerance ............................................................................................ 90
DS1 (1544 kbit/s) Jitter Tolerance ......................................................................................... 90
Jitter Tolerance Measurements ............................................................................................. 91
E1 Jitter Transfer Measurements .......................................................................................... 93
DS1 Jitter Transfer Measurements ........................................................................................ 93
TU-12 Standard Pointer Test Sequences .............................................................................. 96
VT1.5 Standard Pointer Test Sequences .............................................................................. 98
Boundary Scan Schematic .................................................................................................. 100
TEMx28 TXC-04222 376-Lead Plastic Ball Grid Array Package ......................................... 239
Proprietary TranSwitch Corporation Information for use Solely by its Customers
LIST OF FIGURES
DATA SHEET
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Page
TXC-04222-MB, Ed. 6
TXC-04222
TEMx28
June 2003