TXC-04222-AIOG Transwitch Corporation, TXC-04222-AIOG Datasheet - Page 25

• Manufacturer Part Number: TXC-04222-AIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-04222-AIOG

• Screening Level: Industrial
• Package Type: BGA
• Lead Free Status / Rohs Status: Not Compliant

Symbol Lead No. I/O/P
VTFB15
MICROPROCESSOR BUS INTERFACE SELECTION
MICROPROCESSOR BUS INTERFACE - SPLIT BUS FOR MOTOROLA (M) OR INTEL (I)
ABUST
VTFB2
Symbol
A(14-0)
Symbol
MOTO
AB6, AA7,
AB7, AA8,
AA9, AB9,
Lead No.
AB8, Y9,
Y8, W9,
W1
Lead No.
U1
T3
AA10,
Proprietary TranSwitch Corporation Information for use Solely by its Customers
AB10
W10,
W11,
Y10,
Y12
O
O
I
I/O/P
I/O/P
I
I
CMOS3V
CMOS3V
TTL3Vp Add Bus Timing Select: A low selects the add bus timing mode. In this
Type
4 mA
4 mA
TTL3V Motorola Mode: The following table lists the bus selection options.
TTL3V
Type
Type
Transmit VT1.5 Framing Pulse. Positive one clock cycle pulse that is
used when the VT/TU line interface is selected for a channel. The pulse
determines the start of the VT1.5/TU-11 multiframe in the transmit direction
for Add Bus B. The pulse occurs even when no VT/TU line interface is
selected (as long as Add Bus B is active). The pulse is clocked out on the ris-
ing edge of the TVTCn clock when control bit TnCLKI (bit 3, register X+002H)
is a 0.
Transmit VT2 Framing Pulse. Positive one clock cycle pulse that is used
when the VT/TU line interface is selected for a channel. The pulse deter-
mines the start of the VT2/TU-12 multiframes in the transmit direction for Add
Bus B. The pulse occurs even when no VT/TU line interface is selected (as
long as Add Bus B is active). The pulse is clocked out on the rising edge of
the TVTCn clock when control bit TnCLKI (bit 3, register X+002H) is a 0.
timing mode, the drop and add bus timing signals are independent of
each other. A high selects the drop bus timing mode. In this timing mode,
the add signals (Add bus clock, SPE and C1J1V1 signals) are derived
from the like-named drop bus.
Note: The add bus timing mode must be selected when any of the chan-
nels are assigned to a VT/TU interface. In addition, the J1 and V1 pulses
must be fixed regarding their locations. This restriction is required,
because the TEMx28 provides the downstream circuitry with timing infor-
mation. This lead is pulled high by an internal pull-up to VDD2.
MOTO
L
H
Address Bus (Motorola/Intel Buses): These address line inputs
are used for accessing memory map locations for a read/write cycle.
A14 (lead AB6) is the most significant bit.
DATA SHEET
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Intel bus interface
Motorola bus interface
Action
Name/Function
Name/Function
Name/Function
TXC-04222-MB, Ed. 6
TXC-04222
TEMx28
June 2003