TXC-04222-AIOG Transwitch Corporation, TXC-04222-AIOG Datasheet - Page 69

• Manufacturer Part Number: TXC-04222-AIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-04222-AIOG

• Screening Level: Industrial
• Package Type: BGA
• Lead Free Status / Rohs Status: Not Compliant

The ITU-T defined 16-byte message consists of an alignment signal of (10000000 00000000) in the most sig-
nificant bit (bit 1) of the message. The remaining 7 bits in each byte carry a data message, as illustrated below.
The J2 16-byte message comparison works according to the following steps:
1. The microprocessor-written J2 byte segment should be initialized with a 16-byte message before enabling
2. The J2 message comparison function is then enabled (A/BRnJ2S0 = 1; A/BRnJ2S1 = 0) and immediately
3. The incoming trace message is received, and the J2 comparison circuit searches for the J2 alignment pat-
4. J2 alignment pattern is found and the Received stable trace message locations are updated with this
5. The incoming trace message is then checked for three consecutive 16-byte message repeats.
6. If an error occurs before step 5 is completed, the sequence repeats, starting at step 3 (searching for the
7. If the incoming trace message repeats three times in a row (after the alignment pattern is detected) without
the J2 message comparison function.
the J2 Loss of Lock alarm will be active (A/BnJ2LOL = 1) and the J2 Trace Identifier Mismatch alarm will be
inactive (A/BnJ2TIM = 0). This is the first step in the sequence - to initialize these alarms.
tern (Bit 1: 1000...0 pattern).
incoming trace message.
alignment pattern).
an error then this is an in-lock condition, and the J2 Loss of Lock alarm is reset (A/BnJ2LOL = 0). Note that
at this time the J2 mismatch alarm is still inactive (A/BnJ2TIM =0).
(bit 1, X+010H)
(bit 1, X+080H)
ARnJ2S1
BRnJ2S1
1
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(bit 0, X+010H)
(bit 0, X+080H
Bit
ARnJ2S0
BRnJ2S0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ITU-T 16-Byte J2 Message Format
Receive J2 segment for channel n is configured for the 64-byte J2
message size with alignment only. Receiving an ASCII CR/LF will
synchronize an internal counter so that the next character after the
last LF character will be written into the starting address of the 64
byte segment. The J2 alarms are disabled.
2
3
DATA SHEET
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16-Byte J2 Message
4
5
Action
6
7
8
TXC-04222-MB, Ed. 6
TXC-04222
TEMx28
June 2003