TXC-04222-AIOG Transwitch Corporation, TXC-04222-AIOG Datasheet - Page 75

• Manufacturer Part Number: TXC-04222-AIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-04222-AIOG

• Screening Level: Industrial
• Package Type: BGA
• Lead Free Status / Rohs Status: Not Compliant

Interface Rate Selection
The line interface rate is selected according to the following table:
VT/TU Interface
The VT/TU interface is selected when control bits TnLINT1/0 (bits 7 and 6, X+002H) are set to 11. The
TnSEL1/0 (bits 1 and 0, X+006H) and RnSEL (bit 2, X+006H) control bits determine the drop buses and add
buses from which a VT/TU is dropped and added. The VT/TU interface is not valid for dual unidirectional ring
mode of operation (TnSEL1/0 are 11). Four framing pulse lead references are provided: VTA1.5 (VT1.5s for A
add bus), VTA2 (VT2s for A add bus, VTB1.5 (VT1.5s for B add bus) and VT2 (VTs for B add bus). The over-
head byte option associated with this interface is selected according to the following table:
CODEC
When the rail interface is selected, the CODEC may be configured for the AMI code, or B8ZS/HDB3. When
control bit TnB8ZS (bit 2, X+002H) is set to 0, the CODEC is configured for the AMI line code for both the DS1
and E1 line rates. When this control bit is set to 1, the B8ZS line code is selected for the DS1 line rate, and the
HDB3 line code is selected for the E1 rate. A coding error is processed in the following way:
• A string of 16 or more zeros is counted as a coding violation when the line code is AMI (DS1 or E1).
• A string of more than 4 zeros is counted as a coding violation when the line code is HDB3 (E1).
• A string of more than 8 zeros is counted as a coding violation when the line rate is B8Zs (DS1).
Coding violation are counted in a 16 bit counter in addition to one second counters. When the interface for
channel n is selected for a NRZ interface, the negative Rail lead may be used to input either an external loss of
signal indication or external coding violations. When control bit EXnLOS (bit 1, X+003H) is set to 0, external
coding may be counted. When set to 1, an external loss of signal may be inputted. An external loss of signal
indication must be present for a minimum of 8 clock cycles (DS1 or E1). The active sense associated with the
external loss of signal indication is controlled by control bit EXnLOSP (bit 0, X+003H). When control bit
EXnLOSP is a 1, the sense is active high. External violations
TCLKn edge occurs. TCLKn edge selection is done with control bit TnCLKI
(bit 1, X+007H)
TnVTVC
Proprietary TranSwitch Corporation Information for use Solely by its Customers
0
1
(bit 4, X+002H)
TnE1SL
0
1
Gapped output clock. The overhead bytes V5, J2, N2, and K4, in the data
stream are not clocked in. The clock is gapped during the overhead byte
times.
Symmetrical output clock. The overhead bytes in the data stream are not
clocked in except for bits 1 and 2 in the K4 byte. Bits 3 through 8 in the K4
byte are ignored. Bits 1 and 2 are inserted and transmitted from the VT/TU
interface. Bits 1 and 2 define an extended signal label and virtual concatena-
tion information pertaining to the payload.
DS1 rate (1.544 Mbit/s)
E1 rate (2.048 Mbit/s)
DATA SHEET
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Interface Rate Selected
Overhead Byte Access
are counted when TLOSn is high and the selected
.
TXC-04222-MB, Ed. 6
TXC-04222
TEMx28
June 2003