TXC-04222-AIOG Transwitch Corporation, TXC-04222-AIOG Datasheet - Page 184

• Manufacturer Part Number: TXC-04222-AIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-04222-AIOG

• Screening Level: Industrial
• Package Type: BGA
• Lead Free Status / Rohs Status: Not Compliant

June 2003
TEMx28
TXC-04222
TXC-04222-MB, Ed. 6
Address
X+008
X+009
7-5
7-1
Bit
4
3
2
1
0
0
Proprietary TranSwitch Corporation Information for use Solely by its Customers
TnRESET
RnVTVC
Symbol
RnDIEN
RnAISE
RnSAIS
TCnRE
Not used:
Receive VT/TU Overhead Byte Selection: Enabled with the VT/TU
receive line interface is selected. A 0 causes the output clock RVTCn to be
gapped during the four overhead byte times. A 1 causes the clock to be
symmetrical, and enables the four overhead bytes to be clocked out of the
mapper.
Remote Defect Indication Enable: When this bit is set to 1, alarms
detected in the A or B drop side VT/TU selected are enabled to send three
bit RDI (remote payload, server or connectivity defect indication) or single
bit RDI. The alarms for causing RDI are described in the operations section.
Note: The microprocessor may send an RDI independent of the setting of
this control bit. To prevent contention between the internal logic and micro-
processor control, this bit should be written with a 0.
Tandem Connection RDI/ODI Enable: When this bit is set to 1, alarms
detected in the A or B drop side VT/TU selected are enabled to send Tan-
dem Connection RDI and ODI. The alarms for causing TC RDI and ODI
are described in the operations section. Note: The microprocessor may
send an TC RDI (bit 8 in frame 73) or ODI (bit 7 in frame 74) independent
of the setting of this control bit. To prevent contention between the internal
logic and microprocessor control, this bit should be written with a 0.
Receive Line AIS Enable: When this bit is set to 1, alarms detected in the
A or B drop side VT/TU selected are enabled to send receive DS1 or E1
line AIS. The alarms for causing received AIS to be sent are described in
the operations section. Note: The microprocessor may send line AIS
independent of the setting of this control bit. To prevent contention between
the internal logic and microprocessor control, this bit should be written with
a 0.
Receive Line Interface Send AIS: A 1 forces either a DS1 or E1 line AIS
signal to be sent in the receive direction independent of the drop side
alarms for the VT/TU selected.
Not used:
Transmit Reset: A 1 clears all performance counters to zero (saturating)
or the FE/FFFE hex values (8/16 bit non-saturating), and initializes the
internal FIFOs and state machines for the A and B add bus VT/TU channel
selected.
DATA SHEET
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