TXC-04222-AIOG Transwitch Corporation, TXC-04222-AIOG Datasheet - Page 192

• Manufacturer Part Number: TXC-04222-AIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-04222-AIOG

• Screening Level: Industrial
• Package Type: BGA
• Lead Free Status / Rohs Status: Not Compliant

June 2003
TEMx28
TXC-04222
TXC-04222-MB, Ed. 6
CHANNEL n - B SIDE ADD AND DROP BUS CONTROL REGISTER DESCRIPTIONS (n = 1 to 28)
The following control bits and registers are for the A side drop and add buses. Control bits TnSEL1, TnSEL0
and RnSEL determine the drop bus that the data is dropped from, and the add bus(es) data will be added to.
The drop side is the receive side, while the add side is the transmit side.
Address
X+080
X+081
7-6
4-2
1-0
7-1
Bit
5
0
Proprietary TranSwitch Corporation Information for use Solely by its Customers
BRnTCEN
BRnJ2S1
BRnJ2S0
DBCHnR
BRnSL1
BRnSL2
BRnSL3
Symbol
Not used:
B Side Drop Bus Channel n Tandem Connection Enable: A 1 enables
the B side drop bus Tandem Connection feature for the VT/TU selected for
channel n. A 0 disables the TC feature. Please note the Tandem Connec-
tion feature can only be enabled when the J2 byte is configured for a 16
byte message.
B Side Drop Bus Channel n Microprocessor Written Signal Label
Value: The bits written into this register are compared against the
received signal for a mismatch signal label detector. The three bit posi-
tions correspond to the three signal label bits found in bits 5 through 7 in
the V5 byte for the TU/VT selected. Bit 4 in this register corresponds to bit
5 in the V5 byte.
B Side Drop Bus Channel n J2 Byte Mode Selection: The J2 byte is
processed according to the settings in following table. Please note: the
Tandem Connection feature for a channel is disabled with the J2 byte is
configured for a message size of 64 bytes.
BRnJ2S1 BRnJ2S0
Not used:
B Side Drop Channel n Reset: Writing a 1 to this control bit clears all per-
formance counters to zero (saturating) or the FE/FFFE hex values (8/16
bit non-saturating), and initializes the internal FIFOs and state machines
for the B drop bus VT/TU channel selected. It does not clear the control bit
settings, or latched alarms for the channel selected.
0
0
1
1
DATA SHEET
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0
1
0
1
The J2 memory map segment is configured for
16 byte messages. Received bytes are written
into this segment on a rotating basis starting
with an arbitrary address. The J2 message
comparison circuit is disabled.
The J2 memory map segment is configured for
16 byte messages. Received bytes are written
into this segment aligned to the multi frame pat-
tern. The J2 message comparison circuit is
enabled.
The J2 memory map segment is configured for
64 byte messages. Received bytes are written
into this segment on a rotating basis starting
with an arbitrary address.
The J2 memory map segment is configured for
64 byte messages. Received bytes are written
into this segment aligned to CR/LF sequence.
The J2 message comparison circuit is disabled.
Description
Action