TXC-04222-AIOG Transwitch Corporation, TXC-04222-AIOG Datasheet - Page 84

• Manufacturer Part Number: TXC-04222-AIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-04222-AIOG

• Screening Level: Industrial
• Package Type: BGA
• Lead Free Status / Rohs Status: Not Compliant

June 2003
TEMx28
TXC-04222
TXC-04222-MB, Ed. 6
POINTER GENERATION
The VT/TUs that are added to the A and B add buses have fixed pointers references to the V1 pulse derived
from either the drop side for drop bus timing or from the add side for add bus timing. The VT1.5/TU-11 is fixed
with a pointer value equal 78, and for a VT2/TU-12 the pointer is fixed to a value of 105.
V4 Byte
Normally the V4 byte is transmitted with a value equal to 00H. When control bit ATnV4BS (bit 0, X+066H) or
BTnV4BS (bit 0, X+0D6H) is written with a 1, the value written to register X+05EH for the A side and register
X+0CEH for the B side is transmitted instead.
V1 and V2 Bytes
Normally the V1/V2 bytes and the VT/TU payloads and overhead bytes are transmitted with a fixed pointer.
When control bit ATnTPTV (bit 5, X+063H) or BTnTPTV (bit 5, X+0D3H) is written with a 1, the value written to
registers X+05CH and 05DH for the A side and registers X+0CCH and X+0CDH for the B side are transmitted
instead for the V1/V2 bytes. The payload and overhead bytes are still transmitted with fixed the equivalent
fixed pointer values of 78 and 105. This permits a test pointer to be transmitted.
ADD BUSES
The two add buses, A and B, consists of leads supporting the COMBUS interface. The possible interface
selections, including bus timing, are according to the following table.
ABUST
High
High
Low
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ABTE
High
Low
X
DATA SHEET
Add Bus Timing Mode. The output leads consists of data
(A/BA(7-0)), parity, (A/BAPAR), and Add indicator
(A/BADD). The input leads consists of clock (A/BACLK),
C1, J1, and V1 marker pulses (A/BAC1J1V1), and pay-
load indication (A/BASPE).
Drop Bus Timing Mode. The output leads consists of
data (A/BA(7-0)), parity, (A/BAPAR), Add indicator
(A/BADD), clock (A/BACLK), C1, J1, and V1 marker
pulses (A/BAC1J1V1), and payload indication
(A/BASPE). The clock, C1J1V1, and SPE signals are
derived from their liked name drop bus. The V1 pulse is
derived from either the V1 pulse present in the C1J1V1
signal, or from the H4 byte detectors.
Drop Bus Timing Mode. The output leads consists of
data (A/BA(7-0)), parity, (A/BAPAR), and Add indicator
(A/BADD). The clock (A/BACLK), C1, J1, and V1 marker
pulses (A/BAC1J1V1), and payload indication
(A/BASPE) leads are tristated.
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Add Bus Interfaces