UPD78F0034BGC-8BS-A Renesas Electronics America, UPD78F0034BGC-8BS-A Datasheet - Page 115

• Manufacturer Part Number: UPD78F0034BGC-8BS-A
• Description: MCU 8-Bit 78K0 CISC 32KB Flash 2.5V/3.3V/5V 64-Pin LQFP
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0034BGC-8BS-A

• Package: 64LQFP
• Family Name: 78K0
• Maximum Speed: 12 MHz
• Ram Size: 1 KB
• Program Memory Size: 32 KB
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 51
• Interface Type: 3-Wire/UART
• On-chip Adc: 8-chx10-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 3

(3) Stack pointer (SP)
(a) Interrupt enable flag (IE)
(b) Zero flag (Z)
(c) Register bank select flags (RBS0 and RBS1)
(d) Auxiliary carry flag (AC)
(e) In-service priority flag (ISP)
(f) Carry flag (CY)
This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM
area can be set as the stack area. The internal high-speed RAM areas of each product are as follows.
This flag controls the interrupt request acknowledge operations of the CPU.
When 0, the IE is set to the disable interrupt (DI) state, and only non-maskable interrupt request becomes
acknowledgeable. Other interrupt requests are all disabled.
When 1, the IE is set to the enable interrupt (EI) state and interrupt request acknowledge enable is controlled
with an in-service priority flag (ISP), an interrupt mask flag for various interrupt sources and a priority
specification flag.
The IE is reset (0) upon DI instruction execution or interrupt acknowledgment and is set (1) upon EI instruction
execution.
When the operation result is zero, this flag is set (1). It is reset (0) in all other cases.
These are 2-bit flags to select one of the four register banks.
In these flags, the 2-bit information which indicates the register bank selected by SEL RBn instruction
execution is stored.
If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all other
cases.
This flag manages the priority of acknowledgeable maskable vectored interrupts. When this flag is 0, low-
level vectored interrupt requests specified with a priority specification flag register (PR0L, PR0H, PR1L) (see
19.3 (3) Priority specification flag registers (PR0L, PR0H, PR1L)) are disabled for acknowledgment.
When it is 1, all interrupts are acknowledgeable. Actual request acknowledgment is controlled with the
interrupt enable flag (IE).
This flag stores overflow and underflow upon add/subtract instruction execution. It stores the shift-out value
upon rotate instruction execution and functions as a bit accumulator during bit manipulation instruction
execution.
PD780021A, 780031A, 780021AY, 780031AY
PD780022A, 780032A, 780022AY, 780032AY
PD780023A, 780033A, 780023AY, 780033AY
PD780024A, 780034A, 780024AY, 780034AY
PD78F0034A, 78F0034B, 78F0034AY, 78F0034BY
Table 5-4. Internal High-Speed RAM Area
Part Number
CHAPTER 5 CPU ARCHITECTURE
User’s Manual U14046EJ5V0UD
FD00H to FEFFH
FB00H to FEFFH
Internal High-Speed RAM Area
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