UPD78F0034BGC-8BS-A Renesas Electronics America, UPD78F0034BGC-8BS-A Datasheet - Page 480

• Manufacturer Part Number: UPD78F0034BGC-8BS-A
• Description: MCU 8-Bit 78K0 CISC 32KB Flash 2.5V/3.3V/5V 64-Pin LQFP
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0034BGC-8BS-A

• Package: 64LQFP
• Family Name: 78K0
• Maximum Speed: 12 MHz
• Ram Size: 1 KB
• Program Memory Size: 32 KB
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 51
• Interface Type: 3-Wire/UART
• On-chip Adc: 8-chx10-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 3

478
Instruction Mnemonic
Bit
manipu-
late
Group
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
2. When an area except the internal high-speed RAM area is accessed
AND1
OR1
XOR1
SET1
CLR1
SET1
CLR1
NOT1
2. This clock cycle applies to internal ROM program.
3. n is the number of waits when external memory expansion area is read from.
4. m is the number of waits when external memory expansion area is written to.
register (PCC).
CY, saddr.bit
CY, sfr.bit
CY, A.bit
CY, PSW.bit
CY, [HL].bit
CY, saddr.bit
CY, sfr.bit
CY, A.bit
CY, PSW.bit
CY, [HL].bit
CY, saddr.bit
CY, sfr.bit
CY, A.bit
CY, PSW.bit
CY, [HL].bit
saddr.bit
sfr.bit
A.bit
PSW.bit
[HL].bit
saddr.bit
sfr.bit
A.bit
PSW.bit
[HL].bit
CY
CY
CY
Operands
CHAPTER 24 INSTRUCTION SET
User’s Manual U14046EJ5V0UD
Byte
3
3
2
3
2
3
3
2
3
2
3
3
2
3
2
2
3
2
2
2
2
3
2
2
2
1
1
1
Note 1
6
–
4
–
6
6
–
4
–
6
6
–
4
–
6
4
–
4
–
6
4
–
4
–
6
2
2
2
Clock
8 + n + m
8 + n + m
Note 2
7 + n
7 + n
7 + n
7
7
–
7
7
7
–
7
7
7
–
7
6
8
–
6
6
8
–
6
–
–
–
CY
CY
CY
CY
CY
CY
CY
CY
CY
CY
CY
CY
CY
CY
CY
(saddr.bit)
sfr.bit
A.bit
PSW.bit
(HL).bit
(saddr.bit)
sfr.bit
A.bit
PSW.bit
(HL).bit
CY
CY
CY
CY (saddr.bit)
CY sfr.bit
CY A.bit
CY PSW.bit
CY (HL).bit
CY (saddr.bit)
CY sfr.bit
CY A.bit
CY PSW.bit
CY (HL).bit
CY
CY
CY
CY
CY
1
0
CY
CPU
1
0
1
0
1
0
) selected by the processor clock control
1
0
(saddr.bit)
sfr.bit
A.bit
PSW.bit
(HL).bit
1
0
Operation
Z AC CY
Flag
1
0