UPD78F0034BGC-8BS-A Renesas Electronics America, UPD78F0034BGC-8BS-A Datasheet - Page 183

• Manufacturer Part Number: UPD78F0034BGC-8BS-A
• Description: MCU 8-Bit 78K0 CISC 32KB Flash 2.5V/3.3V/5V 64-Pin LQFP
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0034BGC-8BS-A

• Package: 64LQFP
• Family Name: 78K0
• Maximum Speed: 12 MHz
• Ram Size: 1 KB
• Program Memory Size: 32 KB
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 51
• Interface Type: 3-Wire/UART
• On-chip Adc: 8-chx10-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 3

7.6.2 System clock and CPU clock switching procedure
<1> The CPU is reset by setting the RESET signal to low level after power-on. After that, when reset is released
<2> After the lapse of sufficient time for the V
<3> Upon detection of a decrease of the V
<4> Upon detection of V
Interrupt request signal
This section describes procedure for switching between the system clock and CPU clock.
Caution
by setting the RESET signal to high level, the main system clock starts oscillation. At this time, the oscillation
stabilization time (2
After that, the CPU starts executing instructions at the minimum speed of the main system clock (3.81 s @
8.38 MHz operation).
is rewritten and maximum-speed operation is carried out.
switched to the subsystem clock (which must be in an oscillation stable state).
clock is started. After the lapse of the time required for stabilization of oscillation, PCC is rewritten and the
maximum-speed operation is resumed.
System clock
CPU clock
When the main system clock is stopped and the device is operating on the subsystem clock,
wait until the oscillation stabilization time has been secured by the program before switching
back to the main system clock.
RESET
V
DD
17
DD
/f
X
voltage reset due to an interrupt, 0 is set to the MCC and oscillation of the main system
Figure 7-9. System Clock and CPU Clock Switching
) is secured automatically.
CHAPTER 7 CLOCK GENERATOR
Lowest-
speed
operation
User’s Manual U14046EJ5V0UD
DD
Wait (15.6 ms: @8.38 MHz operation)
Internal reset operation
DD
f
X
voltage due to an interrupt request signal, the main system clock is
voltage to increase to enable operation at maximum speeds, PCC
Highest-
speed
operation
f
X
Subsystem
clock
operation
f
XT
High-speed
operation
f
X
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