UPD78F0034BGC-8BS-A Renesas Electronics America, UPD78F0034BGC-8BS-A Datasheet - Page 441
UPD78F0034BGC-8BS-A
Manufacturer Part Number
UPD78F0034BGC-8BS-A
Description
MCU 8-Bit 78K0 CISC 32KB Flash 2.5V/3.3V/5V 64-Pin LQFP
Manufacturer
Renesas Electronics America
Datasheet
1.UPD78F0034BGK-9ET-A.pdf
(605 pages)
Specifications of UPD78F0034BGC-8BS-A
Package
64LQFP
Family Name
78K0
Maximum Speed
12 MHz
Ram Size
1 KB
Program Memory Size
32 KB
Operating Supply Voltage
2.5|3.3|5 V
Data Bus Width
8 Bit
Program Memory Type
Flash
Number Of Programmable I/os
51
Interface Type
3-Wire/UART
On-chip Adc
8-chx10-bit
Operating Temperature
-40 to 85 °C
Number Of Timers
3
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address at 0000H and 0001H by RESET input.
is set to the status shown in Table 22-1. Each pin has high impedance during reset input or during oscillation
stabilization time just after reset release.
of oscillation stabilization time (2
a reset and program execution starts after the lapse of oscillation stabilization time (2
22-4).
The following two operations are available to generate the reset signal.
(1) External reset input via RESET pin
(2) Internal reset by watchdog timer program loop time detection
External reset and internal reset have no functional differences. In both cases, program execution starts at the
When a low level is input to the RESET pin or the watchdog timer overflows, a reset is applied and each hardware
When a high level is input to the RESET pin, the reset is released and program execution starts after the lapse
Cautions 1. For an external reset, input a low level for 10 s or more to the RESET pin.
Count clock
RESET
2. During reset input, main system clock oscillation remains stopped but subsystem clock
3. When the STOP mode is released by reset, the STOP mode contents are held during reset
oscillation continues.
input. However, the port pin becomes high impedance.
17
Figure 22-1. Reset Function Block Diagram
/f
X
CHAPTER 22 RESET FUNCTION
). The reset applied by watchdog timer overflow is automatically released after
User’s Manual U14046EJ5V0UD
Reset controller
Watchdog timer
Stop
Overflow
17
/f
X
) (see Figures 22-2 to
Reset signal
Interrupt function
439
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