UPD78F0034BGC-8BS-A Renesas Electronics America, UPD78F0034BGC-8BS-A Datasheet - Page 350

• Manufacturer Part Number: UPD78F0034BGC-8BS-A
• Description: MCU 8-Bit 78K0 CISC 32KB Flash 2.5V/3.3V/5V 64-Pin LQFP
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0034BGC-8BS-A

• Package: 64LQFP
• Family Name: 78K0
• Maximum Speed: 12 MHz
• Ram Size: 1 KB
• Program Memory Size: 32 KB
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 51
• Interface Type: 3-Wire/UART
• On-chip Adc: 8-chx10-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 3

(2) IIC status register 0 (IICS0)
Address: FFA9H After reset: 00H
348
Symbol
IICS0
This register indicates the status of I
IICS0 is read by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears IICS0 to 00H.
Note This register is also cleared when a bit manipulation instruction is executed for bits other than IICS0.
Remark LREL0: Bit 6 of IIC control register 0 (IICC0)
Condition for clearing (MSTS0 = 0)
• When a stop condition is detected
• When ALD0 = 1 (arbitration loss)
• Cleared by LREL0 = 1 (exit from communications)
• When IICE0 changes from 1 to 0 (operation stop)
• When RESET is input
Condition for clearing (ALD0 = 0)
• Automatically cleared after IICS0 is read
• When IICE0 changes from 1 to 0 (operation stop)
• When RESET is input
Condition for clearing (EXC0 = 0)
• When a start condition is detected
• When a stop condition is detected
• Cleared by LREL0 = 1 (exit from communications)
• When IICE0 changes from 1 to 0 (operation stop)
• When RESET is input
MSTS0
MSTS0
EXC0
ALD0
<7>
CHAPTER 18 SERIAL INTERFACE IIC0 ( PD780024AY, 780034AY SUBSERIES ONLY)
0
1
0
1
0
1
IICE0:
Slave device status or communication standby status
Master device communication status
This status means either that there was no arbitration or that the arbitration result was a “win”.
This status indicates the arbitration result was a “loss”. MSTS0 is cleared.
Extension code was not received.
Extension code was received.
Bit 7 of IIC control register 0 (IICC0)
ALD0
<6>
Figure 18-6. Format of IIC Status Register 0 (IICS0) (1/3)
R
EXC0
<5>
2
C.
User’s Manual U14046EJ5V0UD
COI0
<4>
Note
Detection of extension code reception
Detection of arbitration loss
Master device status
TRC0
<3>
Condition for setting (MSTS0 = 1)
• When a start condition is generated
Condition for setting (ALD0 = 1)
• When the arbitration result is a “loss”.
Condition for setting (EXC0 = 1)
• When the higher 4 bits of the received
address data are either “0000” or “1111”
(set at the rising edge of the eighth clock).
ACKD0
<2>
STD0
<1>
SPD0
<0>