UPD78F0034BGC-8BS-A Renesas Electronics America, UPD78F0034BGC-8BS-A Datasheet - Page 433

• Manufacturer Part Number: UPD78F0034BGC-8BS-A
• Description: MCU 8-Bit 78K0 CISC 32KB Flash 2.5V/3.3V/5V 64-Pin LQFP
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0034BGC-8BS-A

• Package: 64LQFP
• Family Name: 78K0
• Maximum Speed: 12 MHz
• Ram Size: 1 KB
• Program Memory Size: 32 KB
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 51
• Interface Type: 3-Wire/UART
• On-chip Adc: 8-chx10-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 3

21.1 Standby Function and Configuration
21.1.1 Standby function
available.
(1) HALT mode
(2) STOP mode
is set are held. The I/O port output latches and output buffer statuses are also held.
The standby function is designed to decrease power consumption of the system. The following two modes are
In either of these two modes, all the contents of registers, flags and data memory just before the standby mode
Cautions 1. The STOP mode can be used only when the system operates with the main system clock
HALT instruction execution sets the HALT mode. The HALT mode stops the CPU operation clock. The system
clock oscillator continues oscillating. In this mode, power consumption is not decreased as much as in the STOP
mode. However, the HALT mode is effective to restart operation immediately upon an interrupt request and to
carry out intermittent operations.
STOP instruction execution sets the STOP mode. In the STOP mode, the main system clock oscillator stops,
stopping the whole system, thereby considerably reducing the CPU power consumption.
Data memory low-voltage hold (down to V
memory contents with ultra-low power consumption. Because this mode can be released upon an interrupt
request, it enables intermittent operations to be carried out.
However, because a wait time is required to stabilize oscillation after the STOP mode is released, select the HALT
mode if it is necessary to start processing immediately upon an interrupt request.
2. When operation is transferred to the STOP mode, be sure to stop operation of the peripheral
3. The following sequence is recommended for reducing the power consumption of the A/D
(subsystem clock oscillation cannot be stopped). The HALT mode can be used with either
the main system clock or the subsystem clock.
hardware operating with the main system clock before executing the STOP instruction.
converter when the standby function is used: First clear bit 7 (ADCS0) of A/D converter mode
register 0 (ADM0) to 0 to stop the A/D conversion operation, and then execute the HALT or
STOP instruction.
CHAPTER 21 STANDBY FUNCTION
User’s Manual U14046EJ5V0UD
DD
= 1.6 V) is possible. Thus, the STOP mode is effective to hold data
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