UPD78F0034BGC-8BS-A Renesas Electronics America, UPD78F0034BGC-8BS-A Datasheet - Page 366

• Manufacturer Part Number: UPD78F0034BGC-8BS-A
• Description: MCU 8-Bit 78K0 CISC 32KB Flash 2.5V/3.3V/5V 64-Pin LQFP
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0034BGC-8BS-A

• Package: 64LQFP
• Family Name: 78K0
• Maximum Speed: 12 MHz
• Ram Size: 1 KB
• Program Memory Size: 32 KB
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 51
• Interface Type: 3-Wire/UART
• On-chip Adc: 8-chx10-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 3

18.5.13 Communication reservation
to enable transmission of a start condition when the bus is released. There are two modes under which the bus is
not used.
is automatically generated and wait status is set. When the bus release is detected (when a stop condition is detected),
writing to IIC shift register 0 (IIC0) causes the master address transfer to start. At this point, bit 4 (SPIE0) of IICC0
should be set (1).
according to the bus status.
after SST0 is set and the wait time elapses.
the settings for bits 3 and 0 (SMC0 and CL00) in IIC transfer clock select register 0 (IICCL0).
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To start master device communications when not currently using a bus, a communication reservation can be made
• When arbitration results in neither master nor slave operation
• When an extension code is received and slave operation is disabled (ACK is not returned and the bus was
If bit 1 (STT0) of IICC0 is set (1) while the bus is not used (after a stop condition is detected), a start condition
When STT0 has been set (1), the operation mode (as start condition or as communication reservation) is determined
• If the bus has been released ........................................... a start condition is generated
• If the bus has not been released (standby mode) .......... communication reservation
Check whether the communication reservation operates or not by using MSTS0 (bit 7 of IIC status register 0 (IICS0))
The wait periods, which should be set via software, are listed in Table 18-5. These wait periods can be set via
Figure 18-18 shows the communication reservation timing.
released when bit 6 (LREL0) of IIC control register 0 (IICC0) was set to 1).
CHAPTER 18 SERIAL INTERFACE IIC0 ( PD780024AY, 780034AY SUBSERIES ONLY)
SMC0
0
0
1
1
Table 18-5. Wait Periods
User’s Manual U14046EJ5V0UD
CL00
0
1
0
1
26 clocks
46 clocks
16 clocks
Wait Period