UPD78F0034BGC-8BS-A Renesas Electronics America, UPD78F0034BGC-8BS-A Datasheet - Page 221

• Manufacturer Part Number: UPD78F0034BGC-8BS-A
• Description: MCU 8-Bit 78K0 CISC 32KB Flash 2.5V/3.3V/5V 64-Pin LQFP
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0034BGC-8BS-A

• Package: 64LQFP
• Family Name: 78K0
• Maximum Speed: 12 MHz
• Ram Size: 1 KB
• Program Memory Size: 32 KB
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 51
• Interface Type: 3-Wire/UART
• On-chip Adc: 8-chx10-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 3

9.2 Configuration of 8-Bit Timer/Event Counters 50, 51
(1) 8-bit timer counter 5n (TM5n: n = 0, 1)
(2) 8-bit timer compare register 5n (CR5n: n = 0, 1)
8-bit timer/event counters 50, 51 consist of the following hardware.
<1> RESET input
<2> When TCE5n is cleared
<3> When TM5n and CR5n match in the clear & start mode entered on a match between TM5n and CR5n.
Note An error may occur in the count. Select a count clock with a high/low-level waveform longer than two cycles
Caution
Caution
TM5n is an 8-bit read-only register that counts the count pulses.
The counter is incremented in synchronization with the rising edge of the count clock.
When TM50 and TM51 can be connected in cascade and used as a 16-bit timer, they can be read by a 16-bit
memory manipulation instruction. However, since they are connected by an internal 8-bit bus, TM50 and TM51
are read separately twice in that order. Thus, take reading during the count change into consideration and
compare them by reading twice. When the count value is read during operation, the count clock input is
temporarily stopped
00H.
When CR5n is used as a compare register in other than PWM mode, the value set in CR5n is constantly compared
with the 8-bit timer counter 5n (TM5n) count value, and an interrupt request (INTTM5n) is generated if they match.
In PWM mode, the TO5n pin goes to the active level by the overflow of TM5n. When the values of TM5n and
CR5n match, the TO5n pin goes to the inactive level.
It is possible to rewrite the value of CR5n within 00H to FFH during a count operation.
When TM50 and TM51 can be connected in cascade and used as a 16-bit timer, CR50 and CR51 operate as
a 16-bit compare register. This register compares the count value with the register value, and if the values match,
an interrupt request (INTTM50) is generated. The INTTM51 interrupt request is also generated at this time. Thus,
mask the INTTM51 interrupt request. CR5n is set by an 8-bit memory manipulation instruction. RESET input
makes CR5n undefined.
Remark n = 0, 1
of the CPU clock.
In cascade connection mode, the count value is reset to 0000H when TCE50 of the lowest timer
is cleared.
In cascade connection mode, stop the timer operation before setting data.
Timer counter
Register
Timer input
Timer output
Control registers
Table 9-1. Configuration of 8-Bit Timer/Event Counters 50, 51
Note
Item
, and then the count value is read. In the following situations, count value is cleared to
CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 50, 51
8-bit timer counter 5n (TM5n)
8-bit timer compare register 5n (CR5n)
TI5n
TO5n
Timer clock select register 5n (TCL5n)
8-bit timer mode control register 5n (TMC5n)
Port mode register 7 (PM7)
Port 7 (P7)
User’s Manual U14046EJ5V0UD
Configuration
219