UPD78F0034BGC-8BS-A Renesas Electronics America, UPD78F0034BGC-8BS-A Datasheet - Page 180

• Manufacturer Part Number: UPD78F0034BGC-8BS-A
• Description: MCU 8-Bit 78K0 CISC 32KB Flash 2.5V/3.3V/5V 64-Pin LQFP
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0034BGC-8BS-A

• Package: 64LQFP
• Family Name: 78K0
• Maximum Speed: 12 MHz
• Ram Size: 1 KB
• Program Memory Size: 32 KB
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 51
• Interface Type: 3-Wire/UART
• On-chip Adc: 8-chx10-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 3

7.5 Clock Generator Operations
standby mode.
(PCC).
(a) Upon generation of the RESET signal, the lowest speed mode of the main system clock (3.81 s @ 8.38 MHz
(b) With the main system clock selected, one of the five levels of minimum instruction execution time (0.166 s, 0.333
(c) With the main system clock selected, two standby modes, the STOP and HALT modes, are available. To reduce
(d) PCC can be used to select the subsystem clock and to operate the system with low power consumption (122
(e) With the subsystem clock selected, main system clock oscillation can be stopped via PCC. The HALT mode
(f)
178
The clock generator generates the following types of clocks and controls the CPU operating mode including the
• Main system clock
• Subsystem clock
• CPU clock
• Clock to peripheral hardware
The following clock generator functions and operations are determined by the processor clock control register
Note Expanded-specification products of PD780024A, 780034A Subseries only
operation) is selected (PCC = 04H). Main system clock oscillation stops while a low level is applied to the RESET
pin.
MHz operation) can be selected by setting PCC.
power consumption in the STOP mode, the subsystem clock feedback resistor can be disconnected to stop the
subsystem clock.
can be used. However, the STOP mode cannot be used. (Subsystem clock oscillation cannot be stopped.)
The main system clock is divided and supplied to the peripheral hardware. The subsystem clock is supplied to
the watch timer and clock output functions only. Thus the watch function and the clock output function can also
be continued in the standby state. However, since all other peripheral hardware operate with the main system
clock, the peripheral hardware also stops if the main system clock is stopped (except external input clock
operation).
s, 0.666 s, 1.33 s, 2.66 s: @ 12 MHz operation
s @ 32.768 kHz operation).
f
CPU
f
XT
f
X
CHAPTER 7 CLOCK GENERATOR
User’s Manual U14046EJ5V0UD
Note
, 0.238 s, 0.476 s, 0.954 s, 1.90 s, 3.81 s: @ 8.38