UPD78F0034BGC-8BS-A Renesas Electronics America, UPD78F0034BGC-8BS-A Datasheet - Page 218

• Manufacturer Part Number: UPD78F0034BGC-8BS-A
• Description: MCU 8-Bit 78K0 CISC 32KB Flash 2.5V/3.3V/5V 64-Pin LQFP
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0034BGC-8BS-A

• Package: 64LQFP
• Family Name: 78K0
• Maximum Speed: 12 MHz
• Ram Size: 1 KB
• Program Memory Size: 32 KB
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 51
• Interface Type: 3-Wire/UART
• On-chip Adc: 8-chx10-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 3

216
(8) Capture operation
(9) Compare operation
(10) Edge detection
(11) STOP mode or main system clock stop mode setting
<1> If TI00 is specified as the valid edge of the count clock, a capture operation by the capture register specified
<2> If both the rising and falling edges are selected as the valid edges of TI00, capture is not performed.
<3> To ensure the reliability of the capture operation, the capture trigger requires a pulse longer than two cycles
<4> The capture operation is performed at the fall of the count clock. An interrupt request input (INTTM0n),
<1> When the 16-bit timer capture/compare register (CR00/CR01) is overwritten during timer operation, match
<2> The capture operation may not be performed for CR00/CR01 set in compare mode even if a capture trigger
<1> If the TI00 pin or the TI01 pin is high level immediately after system reset and the rising edge or both the
<2> The sampling clock used to remove noise differs when a TI00 valid edge is used as the count clock and
Except when TI00, TI01 input is selected, stop the timer operation before setting STOP mode or main system
clock stop mode; otherwise the timer may malfunction when the main system clock starts.
as the trigger for TI00 is not possible.
of the count clock selected by prescaler mode register 0 (PRM0).
however, occurs at the rise of the next count clock.
interrupt may be generated or the clear operation may not be performed normally if that value is close to
or large than the timer value.
is input.
rising and falling edges are specified as the valid edge for the TI00 pin or TI01 pin to enable 16-bit timer
counter 0 (TM0) operation, a rising edge is detected immediately. Be careful when pulling up the TI00 pin
or the TI01 pin. However, the rising edge is not detected at restart after the operation has been stopped
once.
when it is used as a capture trigger. In the former case, the count clock is f
count clock is selected by prescaler mode register 0 (PRM0). The capture operation is not performed until
the valid edge is sampled and the valid level is detected twice, thus eliminating noise with a short pulse
width.
Rising edge detection
Count clock
Figure 8-31. CR01 Capture Operation with Rising Edge Specified
INTTM01
CR01
TM0
TI00
CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0
N
3
User’s Manual U14046EJ5V0UD
N
2
N
1
N
N
X
/2
N + 1
3
, and in the latter case the