UPD78F0034BGC-8BS-A Renesas Electronics America, UPD78F0034BGC-8BS-A Datasheet - Page 522

• Manufacturer Part Number: UPD78F0034BGC-8BS-A
• Description: MCU 8-Bit 78K0 CISC 32KB Flash 2.5V/3.3V/5V 64-Pin LQFP
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0034BGC-8BS-A

• Package: 64LQFP
• Family Name: 78K0
• Maximum Speed: 12 MHz
• Ram Size: 1 KB
• Program Memory Size: 32 KB
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 51
• Interface Type: 3-Wire/UART
• On-chip Adc: 8-chx10-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 3

Subsystem Clock Oscillator Characteristics (T
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the broken
520
Crystal
resonator
External
clock
Resonator
Remark For the resonator selection and oscillator constant of the subsystem clock, customers are required to
CHAPTER 26 ELECTRICAL SPECIFICATIONS (CONVENTIONAL PRODUCTS: f
2. Time required to stabilize oscillation after V
2. The subsystem clock oscillator is designed as a low-amplitude circuit for reducing power
either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation.
Recommended Circuit
lines in the above figure to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as V
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
consumption, and is more prone to malfunction due to noise than the main system clock
oscillator. Particular care is therefore required with the wiring method when the subsystem
clock is used.
XT2 XT1 V
XT2
R
C4
XT1
C3
SS1
Oscillation
frequency (f
Oscillation
stabilization time
XT1 input
frequency (f
XT1 input
high-/low-level width
(t
XTH
, t
Parameter
XTL
User’s Manual U14046EJ5V0UD
)
XT
XT
)
)
Note 1
Note 1
Note 2
DD
A
reaches oscillation voltage range MIN.
= 40 to +85 C, V
4.0 V
1.8 V
Conditions
V
V
DD
DD
5.5 V
4.0 V
DD
= 1.8 to 5.5 V)
MIN.
12
32
32
X
= 1.0 TO 8.38 MHz)
32.768
TYP.
1.2
MAX.
38.5
15
35
10
2
SS1
.
Unit
kHz
kHz
s
s