UPD78F0034BGC-8BS-A Renesas Electronics America, UPD78F0034BGC-8BS-A Datasheet - Page 407

• Manufacturer Part Number: UPD78F0034BGC-8BS-A
• Description: MCU 8-Bit 78K0 CISC 32KB Flash 2.5V/3.3V/5V 64-Pin LQFP
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0034BGC-8BS-A

• Package: 64LQFP
• Family Name: 78K0
• Maximum Speed: 12 MHz
• Ram Size: 1 KB
• Program Memory Size: 32 KB
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 51
• Interface Type: 3-Wire/UART
• On-chip Adc: 8-chx10-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 3

(1) Interrupt request flag registers (IF0L, IF0H, IF1L)
Address: FFE0H After reset: 00H R/W
Symbol
IF0L
Address: FFE1H After reset: 00H R/W
Symbol
IF0H
Address: FFE2H After reset: 00H R/W
Symbol
IF1L
Cautions 1. The WDTIF flag is R/W enabled only when the watchdog timer is used as the interval timer.
The interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction
is executed. They are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request
or upon application of RESET input.
IF0L, IF0H, and IF1L are set by a 1-bit or 8-bit memory manipulation instruction. When IF0L and IF0H are
combined to form 16-bit register IF0, they are set by a 16-bit memory manipulation instruction.
RESET input clears these registers to 00H.
Notes 1. Incorporated only in the PD780024AY, 780034AY Subseries. Be sure to clear 0 for the PD780024A,
2. Incorporated only in the PD780024A, 780034A Subseries. Be sure to clear 0 for the PD780024AY,
2. Be sure to clear bits 3 to 7 of IF1L to 0.
3. When operating a timer, serial interface, or A/D converter after standby release, run it once
4. When an interrupt is acknowledged, the interrupt request flag is automatically cleared, and
5. Use the 1-bit memory manipulation instruction (CLR1) for manipulating the flag of the
780034A Subseries.
780034AY Subseries.
Figure 19-2. Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L)
TMIF51
XXIFX
STIF0
<7>
<7>
If watchdog timer mode 1 is used, set the WDTIF flag to 0.
after clearing an interrupt request flag. An interrupt request flag may be set by noise.
then processing of the interrupt routine is started.
interrupt request flag register. Use the bit manipulation instruction such as “IF0L.0 = 0;”
or “_asm(“clr1 IF0L, 0”);” for describing in C language because the compiled assembler
needs to be the 1-bit memory manipulation instruction (CLR1).
If a program is described in C language using an 8-bit memory manipulation instruction
such as “IF0L & = 0xfe;” and compiled, the assembler of the following three instructions
is described.
In this case, at the timing between “mov a, IF0L” and “mov IF0L, a”, if the request flag of
another bit of the identical interrupt request flag register is set to 1, it is cleared to 0 by
“mov IF0L, a”. Therefore, care must be exercised when using an 8-bit memory manipulation
instruction in C language.
7
0
0
1
mov
and
mov
No interrupt request signal is generated
Interrupt request signal is generated, interrupt request status
TMIF50
SRIF0
<6>
<6>
6
0
a, IF0L
a, #0FEH
IF0L, a
CHAPTER 19 INTERRUPT FUNCTIONS
SERIF0
TMIF01
<5>
<5>
5
0
User’s Manual U14046EJ5V0UD
TMIF00
PIF3
<4>
<4>
4
0
Interrupt request flag
WTIIF
PIF2
<3>
<3>
3
0
IICIF0
KRIF
PIF1
<2>
<2>
<2>
Note 1
CSIIF31
WTIF
PIF0
<1>
<1>
<1>
Note 2
CSIIF30
WDTIF
ADIF0
<0>
<0>
<0>
405