AT32UC3C2256C Atmel Corporation, AT32UC3C2256C Datasheet

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AT32UC3C2256C

Manufacturer Part Number
AT32UC3C2256C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of AT32UC3C2256C

Flash (kbytes)
256 Kbytes
Pin Count
64
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
45
Ext Interrupts
64
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
5
Twi (i2c)
2
Uart
4
Can
2
Lin
4
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
2
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
68
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
13
Input Capture Channels
6
Pwm Channels
14
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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Feature Summary
32-bit load/store RISC architecture
Up to 15 general-purpose 32-bit registers
32-bit Stack Pointer, Program Counter, and Link Register reside in register file
Fully orthogonal instruction set
Pipelined architecture allows one instruction per clock cycle for most instructions
Byte, half-word, word and double word memory access
Fast interrupts and multiple interrupt priority levels
Optional branch prediction for minimum delay branches
Privileged and unprivileged modes enabling efficient and secure Operating Systems
Innovative instruction set together with variable instruction length ensuring industry
leading code density
Optional DSP extention with saturated arithmetic, and a wide variety of multiply
instructions
Optional extensions for Java, SIMD, Read-Modify-Write to memory, and Coprocessors
Architectural support for efficient On-Chip Debug solutions
Optional MPU or MMU allows for advanced operating systems
FlashVault
nontrusted code on the same CPU
support through Secure State for executing trusted code alongside
AVR32
Architecture
Document
32000D–04/2011

AT32UC3C2256C Summary of contents

Page 1

Feature Summary • 32-bit load/store RISC architecture • general-purpose 32-bit registers • 32-bit Stack Pointer, Program Counter, and Link Register reside in register file • Fully orthogonal instruction set • Pipelined architecture allows one instruction per clock ...

Page 2

Introduction AVR32 is a new high-performance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applications, with particular emphasis on low power consumption and high code den- sity. In addition, the instruction set architecture has been tuned to allow for ...

Page 3

Load/store to an address specified by a pointer register with predecrement • Load/store to an address specified by a pointer register with displacement • Load/store to an address specified by a small immediate (direct addressing within a small page) ...

Page 4

Microarchitectures The AVR32 architecture defines different microarchitectures. This enables implementations that are tailored to specific needs and applications. The microarchitectures provide different perfor- mance levels at the expense of area and power consumption. The following microarchitectures are defined: 1.3.1 ...

Page 5

Programming Model This chapter describes the programming model and the set of registers accessible to the user. 2.1 Data Formats The AVR32 processor supports the data types shown in Table 2-1. Type Byte Halfword Word Double Word When any ...

Page 6

AVR32 can access data of size byte, halfword, word and doubleword using dedicated instruc- tions. The memory system can support unaligned accesses for selected load/store instructions in some implementations. Any other unaligned access will cause an address exception. For performance ...

Page 7

Processor States 2.4.1 Normal RISC State The AVR32 processor supports several different execution contexts as shown in page 7. Table 2-3. Priority N/A N/A Mode changes can be made under software control, or ...

Page 8

The secure state is described in chapter 4. 2.5 Entry and Exit Mechanism Table 2-4 on page ...

Page 9

Figure 2-2. Application Bit SP_APP R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC 2.6.2 Register File in AVR32B The AVR32B allows separate register files for the interrupt ...

Page 10

This allows for maximum flexibility in targeting the processor for different application, see Figure 2-4. Application Bit 31 Bit SP_APP R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 ...

Page 11

The Program Counter The Program Counter (PC) contains the address of the instruction being executed. The memory space is byte addressed. With the exception of Java state, the instruction size is a multiple of 2 bytes and the LSB ...

Page 12

Figure 2- Secure State This bit is indicates if the processor is executing in the secure state. For more details, see chap- ter 4. The bit is initialized in ...

Page 13

Table 2- Exception mask When this bit is set, exceptions are masked. Exceptions are enabled otherwise. The bit is auto- matically set when exception processing is initiated or Debug Mode is entered. Software may clear this bit ...

Page 14

R - Java register remap When this bit is set, the addresses of the registers in the register file is dynamically changed. This allows efficient use of the register file registers as a stack. For more details, see chapter 3.. ...

Page 15

The Compliance column describes if the register is Required, Optional or Unused in AVR32A and AVR32B, see Table 2-6. Abbreviation Table 2-7. System Registers Reg # Address Name EVBA ...

Page 16

Table 2-7. System Registers (Continued) Reg # Address Name 24 96 JAVA_LV1 25 100 JAVA_LV2 26 104 JAVA_LV3 27 108 JAVA_LV4 28 112 JAVA_LV5 29 116 JAVA_LV6 30 120 JAVA_LV7 31 124 JTBA 32 128 JBCR 33-63 132-252 Reserved 64 ...

Page 17

Table 2-7. System Registers (Continued) Reg # Address Name 90 360 MPUPSR2 91 364 MPUPSR3 92 368 MPUPSR4 93 372 MPUPSR5 94 376 MPUPSR6 95 380 MPUPSR7 96 384 MPUCRA 97 388 MPUCRB 98 392 MPUBRA 99 396 MPUBRB 100 ...

Page 18

ACBA word aligned. Failing may result in erroneous behaviour. CPUCR - CPU Control Register Register controlling the configuration and behaviour of the CPU. The behaviour of this register is IMPLEMENTATION DEFINED. ...

Page 19

JAVA_LVx - Java Local Variable Registers The Java Extension Module uses these registers to store local variables temporary. JTBA - Java Trap Base Address This register contains the base address to the program code for the trapped Java instructions. JBCR ...

Page 20

MMUCR - MMU Control Register Used to control the MMU and the TLB. The contents and functionality of the register is described in detail in TLBARLO / TLBARHI - MMU TLB Accessed Register Low / High Contains the Accessed bits ...

Page 21

SS_STATUS - Secure State Status Register Register that can be used to pass status or other information from the secure state to the nonse- cure state. Refer to SS_ADRF, SS_ADRR, SS_ADR0, SS_ADR1 - Secure State Address Registers Registers used to ...

Page 22

Table 2-8. Name AT AR MMUT AVR32 22 CONFIG0 Fields (Continued) Bit Description Architecture type Value Semantic 15:13 0 AVR32A 1 AVR32B Other Reserved Architecture Revision. Specifies which revision of the AVR32 12:10 architecture the processor ...

Page 23

Table 2-8. Name Table 2-9 on page 23 Table 2-9. Name IMMU SZ DMMU SZ 32000D–04/2011 CONFIG0 Fields (Continued) Bit Description SIMD instructions implemented Value Semantic SIMD instructions 1 SIMD instructions implemented DSP instructions ...

Page 24

Table 2-9. Name ISET ILSZ AVR32 24 CONFIG1 Fields (Continued) Bit Description Number of sets in ICACHE Value Semantic 19:16 7 128 8 256 9 512 ...

Page 25

Table 2-9. Name IASS DSET 32000D–04/2011 CONFIG1 Fields (Continued) Bit Description Associativity of ICACHE Value Semantic 0 Direct mapped 1 2-way 2 4-way 12:10 3 8-way 4 16-way 5 32-way 6 64-way 7 128-way Number of sets in DCACHE Value ...

Page 26

Table 2-9. Name DLSZ DASS 2.12 Recommended Call Convention The compiler vendor is free to define a call convention, but seen from a hardware point of view, there are some recommendations on how the call convention should be defined. Register ...

Page 27

Java Extension Module The AVR32 architecture can optionally support execution of Java bytecodes by including a Java Extension Module (JEM). This support is included with minimal hardware overhead. Comparing Java bytecode instructions with native AVR32 instructions, we see that ...

Page 28

The AVR32 Java Virtual Machine software loads and controls the execution of the Java classes. The bytecodes are executed in hardware, except for some instructions, for example the instruc- tions that create or manipulate objects. These are trapped and executed ...

Page 29

Java state. This means that the instruction decoder now decodes Java opcodes instead of the normal AVR32 opcodes. Figure 3-3. 32000D–04/2011 Example of running a Java program void ...

Page 30

During execution of the Java program, the Java Extension Module will encounter some byte- codes that are not supported in hardware. The instruction decoder will automatically recognize these bytecodes and switch the processor back into RISC state and at the ...

Page 31

Secure state Revision 3 of the AVR32 architecture introduces a secure execution state. This state is intended to allow execution of a proprietary secret code alongside code of unknown origin and intent on the same processor. For example, a ...

Page 32

When trying to access secure world memories from the nonsecure world, a bus error exception will be raised, and the access will be aborted. Writes to secure system registers from within the nonsecure world will simply be disregarded without ...

Page 33

Figure 4-2. Application Bit SP_APP R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC 4.3 Details on Secure State implementation Refer to the Technical Reference manual for the ...

Page 34

AVR32 34 32000D–04/2011 ...

Page 35

Memory Management Unit The AVR32 architecture defines an optional Memory Management Unit (MMU). This allows effi- cient implementation of virtual memory and large memory spaces. Virtual memory simplifies execution of multiple processes and allows allocation of privileges to different ...

Page 36

The P3 space is also by default segment translated to the physical address range 0x00000000 to 0x1FFFFFFF. By enabling and setting up the MMU, the P3 space becomes page translated. Page translation will override segment translation. The P4 space is ...

Page 37

Figure 5-2. 0xFFFFFFFF 0xE0000000 0xC0000000 0xA0000000 0x80000000 0x00000000 5.2 Understanding the MMU The AVR32 Memory Management Unit (MMU) is responsible for mapping virtual to physical addresses. When a memory access is performed, the MMU translates the virtual ...

Page 38

Virtual Memory Models The MMU provides two different virtual memory models, selected by the Mode (M) bit in the MMU Control Register: • Shared virtual memory, where the same virtual address space is shared between all processes • Private ...

Page 39

TLB Entry Register High Part - TLBEHI The contents of the TLBEHI and TLBELO registers is loaded into the TLB when the tlbw instruc- tion is executed. The TLBEHI register consists of the following fields: • VPN - Virtual ...

Page 40

Table 5-2. AP 000 001 010 011 100 101 110 111 • Size of the page. The following page sizes are provided, see Table 5- • Dirty bit. Set if the ...

Page 41

ITLB IMPLEMENTATION DEFINED whether to use fewer entries. Impementations with a single unified TLB does not use the IRP field. • ILA - Instruction TLB Lockdown Amount. Specified the number of locked down ITLB entries. ...

Page 42

Page Table Organization The MMU leaves the page table organization up to the OS software. Since the page table han- dling and TLB handling is done in software, the OS is free to implement different page table organizations. It ...

Page 43

Translation process The translation process maps addresses from the virtual address space to the physical address space. The addresses are generated as shown in chosen: Table 5-5. Page size data ...

Page 44

The translation process performed by PerformTranslatedAccess( ) can be described as shown in Table Table 5-7. match ← 0; for (i=0; i<TLBentries; i++) if ( Compare(TLB[i] endfor; if (match == 0 ) SignalException(DTLBmiss, accesstype); endif; if (InApplicationMode) if (TLB[ptr] endif; ...

Page 45

An instruction memory access can be described as shown in Table 5-8. If (Segmentation disabled) else endif; 32000D–04/2011 Instruction memory access pseudo-code example If (! PagingEnabled) PerformAccess(cached, write-back); else PerformPagedAccess(VA); if (VA in Privileged space) if (InApplicationMode) SignalException(ITLB Protection, accesstype); ...

Page 46

The translation process performed by PerformTranslatedAccess( ) can be described as as shown in Table 5-9. match ← 0; for (i=0; i<TLBentries; i++) if ( Compare(TLB[i] endfor; if (match == 0 ) SignalException(ITLBmiss); endif; if (InApplicationMode) if (TLB[ptr] endif; endif; ...

Page 47

Operation of the MMU and MMU exceptions The MMU uses both hardware and software mechanisms in order to perform its memory remap- ping operations. The following tasks are performed by hardware: 1. The MMU decodes the virtual address and ...

Page 48

MMU exception handling This chapter describes the software actions that must be performed for MMU-related excep- tions. The hardware actions performed by the exceptions are described in detail in “Description of events in AVR32A” on page 5.3.3.1 ITLB / ...

Page 49

DTLB Modified This exception is issued if a valid memory write operation is performed to a page that has never been written before. This is detected by the Dirty-bit in the matching TLB entry reading zero. 1. Examine the ...

Page 50

AVR32 50 32000D–04/2011 ...

Page 51

Memory Protection Unit The AVR32 architecture defines an optional Memory Protection Unit (MPU). This is a simpler alternative to a full MMU, while at the same time allowing memory protection. The MPU allows the user to divide the memory ...

Page 52

Register space, their addresses are presented in accessed with the mtsr and mfsr instructions. The MPU interface registers are shown below. The suffix n can have the range 0-7, indicating which region the register is associated with. Figure 6-1. ...

Page 53

Size - Size of the protection region. The possible sizes are shown in Table 6-1. Size B’00000 to B’01010 B’01011 B’01100 B’01101 B’01110 B’01111 B’10000 B’10001 B’10010 B’10011 B’10100 B’10101 B’10110 B’10111 B’11000 B’11001 B’11010 B’11011 B’11100 B’11101 B’11110 ...

Page 54

MPU Cacheable Register MPUCRA / MPUCRB The MPUCR registers have one bit per region, indicating if the region is cacheable. If the corre- sponding bit is set, the region is cacheable. The register is written to ...

Page 55

DTLB Protection Violation An DTLB protection violation is issued if a data access violates access permissions. The violat- ing access is not executed. The address of the failing instruction is placed on the system stack. 6.2.2.3 ITLB Miss Violation ...

Page 56

AVR32 56 32000D–04/2011 ...

Page 57

Performance counters 7.1 Overview A set of performance counters let users evaluate the performance of the system. This is useful when scheduling code and performing optimizations. Two configurable event counters are pro- vided in addition to a clock cycle ...

Page 58

The following fields exist in PCCR, see Table 7-1. Bit 23:18 17:12 10:8 6 Other AVR32 58 Table 7-1 on page Performance counter control register Access Name Description Configures which events to count with PCNT1. See ...

Page 59

Monitorable events The following events can be monitored by the performance counters, depending on the setting of CONF0 and CONF1, see Table 7-2. Monitorable events Configure field setting Event monitored and counted Instruction cache miss. Incremented once for each ...

Page 60

Usage The performance counters can be used to monitor several different events and perform different measurements. Some of the most useful are explained below. 7.4.1 Cycles per instruction CONF0: 0x7 (Instruction executed) CPI = CCNT / PCNT0 Cycles-per-instruction (CPI) ...

Page 61

AWSD = PCNT0 / PCNT1 The average writeback stall duration (AWSD) mesures the average number of clock cycles spent stalling due to a full writebuffer. 7.4.7 Fraction of execution time spent stalling due to writeback CONF0: 0x9 (Write buffer full ...

Page 62

AVR32 62 32000D–04/2011 ...

Page 63

Event Processing Due to various reasons, the CPU may be required to abort normal program execution in order to handle special, high-priority events. When handling of these events is complete, normal program execution can be resumed. Traditionally, events that ...

Page 64

Each exception handler has a dedicated handler address, and this address uniquely identifies the exception source. 3. The Mode bits are set to reflect the priority of the accepted event, and the correct regis- ter file ...

Page 65

It is the event source’s responsability to ensure that their events are left pending until accepted by the CPU. 2. When a request is accepted, the Status Register and Program Counter of ...

Page 66

Entry points for events Several different event handler entry points exists. For AVR32A, the reset routine is placed at address 0x8000_0000. This places the reset address in the flash memory area. For AVR32B, the reset routine entry address is ...

Page 67

Table 8-1. Priority and handler addresses for events Priority Handler Address 0x8000_0000 for AVR32A. 1 0xA000_0000 for AVR32B. 2 Provided by OCD system 3 EVBA+0x00 4 EVBA+0x04 5 EVBA+0x08 6 EVBA+0x0C 7 EVBA+0x10 8 Autovectored 9 Autovectored 10 Autovectored 11 ...

Page 68

The addresses of the interrupt routines are calculated by adding the address on the autovector offset bus to the value of the Exception Vector Base Address (EVBA). The INT0, INT1, INT2, INT3, and NMI signals indicate the priority of the ...

Page 69

Unrecoverable Exception The Unrecoverable Exception is generated when an exception request is issued when the Exception Mask (EM) bit in the status register is asserted. The Unrecoverable Exception can not be masked by any bit. The Unrecoverable Exception is ...

Page 70

Bus Error Exception on Data Access The Bus Error on Data Access exception is generated when the data bus detects an error condi- tion. This exception is caused by events unrelated to the instruction stream data written ...

Page 71

INT3 Exception The INT3 exception is generated when the INT3 input line to the core is asserted. The INT3 exception can be masked by the SR[GM] bit, and the SR[I3M] bit. Hardware automatically sets the SR[I3M] bit when accepting ...

Page 72

SR[ SR[ SR[M2:M0] = B’100; SR[I2M SR[I1M SR[I0M EVBA + INTERRUPT_VECTOR_OFFSET; 8.3.1.10 INT1 Exception The INT1 exception is generated when the INT1 input line to the ...

Page 73

INT0 Exception The INT0 exception is generated when the INT0 input line to the core is asserted. The INT0 exception can be masked by the SR[GM] bit, and the SR[I0M] bit. Hardware automatically sets the SR[I0M] bit when accepting ...

Page 74

ITLB Miss Exception The ITLB Miss exception is generated when no TLB entry matches the instruction memory address the Valid bit in a matching entry is 0. *(--SP *(--SP TLBEAR = FAILING_VIRTUAL_ADDRESS; TLBEHI[VPN] = FAILING_PAGE_NUMBER; TLBEHI[I] = ...

Page 75

Breakpoint Exception The Breakpoint exception is issued when a breakpoint instruction is executed, or the OCD breakpoint input line to the CPU is asserted, and SREG[DM] is cleared. An external debugger can optionally assume control of the CPU when ...

Page 76

Data Read Address Exception The Data Read Address Error exception is generated if the address of a data memory read has an illegal alignment. *(--SP *(--SP TLBEAR = FAILING_VIRTUAL_ADDRESS; TLBEHI[VPN] = FAILING_PAGE_NUMBER; SR[ SR[ SR[M2:M0] ...

Page 77

DTLB Write Miss Exception The DTLB Write Miss exception is generated when no TLB entry matches the data memory address of the current write operation the Valid bit in a matching entry is 0. *(--SP *(--SP TLBEAR ...

Page 78

Privilege Violation Exception If the application tries to execute privileged instructions, this exception is issued. The complete list of priveleged instructions is shown in routine, the address of the instruction that caused the exception is stored as the stacked ...

Page 79

DTLB Modified Exception The DTLB Modified exception is generated when a data memory write hits a valid TLB entry, but the Dirty bit of the entry is 0. This indicates that the page is not writable. *(--SP *(--SP TLBEAR ...

Page 80

Supervisor call Supervisor calls are signalled by the application code executing a supervisor call (scall) instruc- tion. The scall instruction behaves differently depending on which context it is called from. This allows scall to be called from other contexts ...

Page 81

Description of events in AVR32B 8.3.2.1 Reset Exception The Reset exception is generated when the reset input line to the CPU is asserted. The Reset exception can not be masked by any bit. The Reset exception resets all synchronous ...

Page 82

TLB Multiple Hit Exception TLB Multiple Hit exception is issued when multiple address matches occurs in the TLB, causing an internal inconsistency. This exception signals a critical error where the hardware undefined state. All interrupts are ...

Page 83

SR[GM EVBA + 0x0C; 8.3.2.7 NMI Exception The NMI exception is generated when the NMI input line to the core is asserted. The NMI excep- tion can not be masked by the SR[GM] bit. However, the ...

Page 84

INT2 Exception The INT2 exception is generated when the INT2 input line to the core is asserted. The INT2 exception can be masked by the SR[GM] bit, and the SR[I2M] bit. Hardware automatically sets the SR[I2M] bit when accepting ...

Page 85

INT0 Exception The INT0 exception is generated when the INT0 input line to the core is asserted. The INT0 exception can be masked by the SR[GM] bit, and the SR[I0M] bit. Hardware automatically sets the SR[I0M] bit when accepting ...

Page 86

ITLB Miss Exception The ITLB Miss exception is generated when no TLB entry matches the instruction memory address the Valid bit in a matching entry is 0. RSR_EX = SR; RAR_EX = PC; TLBEAR = FAILING_VIRTUAL_ADDRESS; TLBEHI[VPN] ...

Page 87

SR[EM SR[GM EVBA + 0x1C; 8.3.2.16 Illegal Opcode This exception is issued when the core fetches an unknown instruction, or when a coprocessor instruction is not acknowledged. When entering the exception routine, the return ...

Page 88

Data Write Address Exception The Data Write Address Error exception is generated if the address of a data memory write has an illegal alignment. RSR_EX = SR; RAR_EX = PC; TLBEAR = FAILING_VIRTUAL_ADDRESS; TLBEHI[VPN] = FAILING_PAGE_NUMBER; SR[ ...

Page 89

DTLB Read Protection Exception The DTLB Protection exception is generated when the data memory read violates the access rights specified by the protection bits of the addressed virtual page. RSR_EX = SR; RAR_EX = PC; TLBEAR = FAILING_VIRTUAL_ADDRESS; TLBEHI[VPN] ...

Page 90

Table 8-3. Privileged Instructions csrf - clear status register flag cache - perform cache operation tlbr - read addressed TLB entry into TLBEHI and TLBELO tlbw - write TLB entry registers into TLB tlbs - search TLB for entry matching ...

Page 91

Floating-point Exception The Floating-point exception is generated when the optional Floating-Point Hardware signals that an IEEE exception occurred, or when another type of error from the floating-point hardware occurred.. RSR_EX = SR; RAR_EX = PC; SR[ SR[J] ...

Page 92

Event priority Several instructions may be in the pipeline at the same time, and several events may be issued in each pipeline stage. This implies that several pending exceptions may be in the pipeline simultaneously. Priorities must therefore be ...

Page 93

AVR32 RISC Instruction Set 9.1 Instruction Set Nomenclature 9.1.1 Registers and Operands the instruction exists, instruction exists, 32000D–04/2011 R{d, s, …} The uppercase ‘R’ denotes a 32-bit (word) register. Rd The lowercase ‘d’ denotes the destination register number. Rs ...

Page 94

This is also ure will 9.1.2 Operator Symbols 9.1.3 Operations 9.1.4 Status Register Flags instructions. AVR32 94 [i:j] Denotes bit immediate value. Some instructions access or use doubleword operands. These operands ...

Page 95

Data Type Extensions 9.1.5 9.1.6 Halfword selectors 9.1.7 Byte selectors 9.1.8 CPU System Registers 32000D–04/2011 M1: Mode bit 1 M2: Mode bit 2 .d Double (64-bit) operation. .w Word (32-bit) operation. .h Halfword (16-bit) operation. .b Byte operation (8-bit) operation. ...

Page 96

Branch conditions Table 9-1. Branch conditions Coding Coding in cond3 in cond4 B’000 B’0000 B’001 B’0001 B’010 B’0010 B’011 B’0011 B’100 B’0100 B’101 B’0101 B’110 B’0110 B’111 B’0111 N/A B’1000 N/A B’1001 N/A B’1010 N/A B’1011 N/A B’1100 N/A ...

Page 97

Instruction Formats This is an overview of the different instruction formats. 9.2.1 Two Register Instructions Opcod 9.2.2 Single Register Instructions 9.2.3 Return and test ...

Page 98

One register and a register pair 9.2.10 One register with k8 immediate and cond4 9.2.11 One register with bit addressing 15 ...

Page 99

Only Opcode 9.2.19 3 registers shifted 9.2.20 3 registers unshifted 9.2.21 DSP ...

Page 100

Registers with w5 and Opcode 9.2.26 Coprocessor 0 load and store ...

Page 101

Register or condition code and K21 9.2.31 No register and k21 9.2.32 Two registers and K16 9.2.33 Register, ...

Page 102

Coprocessor load and store Opc 9.2.37 Coprocessor load and store multiple registers ++/-- 9.2.38 Coprocessor ...

Page 103

Register and bit address 9.2.43 Load and store multiple registers R15 R14 R13 R12 R11 R10 R9 9.2.44 Register, k12 and halfword ...

Page 104

Saturate 9.2.49 3 Registers with Opcode 9.2.50 2 Registers with 9.2.51 2 ...

Page 105

Address and b5[0] 9.2.56 2 register operands 9.2.57 2 register operands and ...

Page 106

Instruction Set Summary 9.3.1 Architecture revision Unless otherwise noted, all instructions are part of revision 1 of the AVR32 architecture. The fol- lowing instructions were added in revision 2, none were removed: • movh Rd, imm • {add, sub, ...

Page 107

Table 9-2. Arithmetic Operations (Continued Rd, Rx, Ry << sa sub C Rd, imm E Rd, imm E Rd, Rs, imm E Rd, imm sub{cond4} E Rd, Rx, Ry tnbz C Rd 9.3.3 Multiplication Operations Table ...

Page 108

DSP Operations Table 9-4. DSP Operations Mnemonics Operands / Syntax Rd, Rx:<part>, addhh.w E Ry:<part> Rd, Rx:<part>, machh.d E Ry:<part> Rd, Rx:<part>, machh.w E Ry:<part> macwh.d E Rd, Rx, Ry:<part> Rd, Rx:<part>, mulhh.w E Ry:<part> mulwh.d E Rd, Rx, ...

Page 109

Table 9-4. DSP Operations (Continued) Rd, Rx:<part>, mulsathh.h E Ry:<part> Rd, Rx:<part>, mulsathh.w E Ry:<part> Rd, Rx:<part>, mulsatrndhh.h E Ry:<part> mulsatrndwh. E Rd, Rx, Ry:<part> w mulsatwh.w E Rd, Rx, Ry:<part> Rd, Rx:<part>, macsathh.w E Ry:<part> 32000D–04/2011 Fractional signed multiply ...

Page 110

Logic Operations Table 9-5. Logic Operations Mnemonics Operands / Syntax C Rd, Rs and E Rd, Rx, Ry << Rd, Rx, Ry >> sa and{cond4} E Rd, Rx, Ry andn C Rd Rd, imm andh ...

Page 111

Bit Operations Table 9-6. Bit Operations Mnemonics Operands / Syntax bfexts E Rd, Rs, o5, w5 bfextu E Rd, Rs, o5, w5 bfins E Rd, Rs, o5, w5 bld E Rd, bp brev C Rd bst E Rd, bp ...

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Shift Operations Table 9-7. Operations Mnemonics Operands / Syntax E Rd, Rx, Ry asr E Rd Rd, Rx, Ry lsl E Rd Rd, Rx, Ry lsr E ...

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Instruction Flow Table 9-8. Instruction Flow Mnemonics Operands / Syntax br{cond3} C disp br{cond4} E disp rjmp C disp acall C disp icall C Rd mcall E Rp[disp] C disp rcall E disp scall C sscall C ret{cond4} C ...

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Data Transfer 9.3.9.1 Move/Load Immediate operations Table 9-9. Move/Load Immediate Operations Mnemonics Operands / Syntax C Rd, imm mov E Rd, imm C Rd Rd, Rs mov{cond4} E Rd, imm movh E Rd, imm 9.3.9.2 Load/Store operations ...

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Table 9-10. Load/Store Operations (Continued) C Rd, Rp++ C Rd, --Rp ld.sh C Rd, Rp[disp] E Rd, Rp[disp] E Rd, Rb[Ri<<sa] ld.sh{cond4} E Rd, Rp[disp] C Rd, Rp++ C Rd, --Rp C Rd, Rp[disp] ld.w E Rd, Rp[disp] E Rd, ...

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Table 9-10. Load/Store Operations (Continued) C Rp++, Rs C --Rp, Rs st.b C Rp[disp Rp[disp Rb[Ri<<sa], Rs st.b{cond4} E Rp[disp Rp++, Rs C --Rp, Rs st Rp[disp Rb[Ri<<sa], ...

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Table 9-10. Load/Store Operations (Continued) stswp.h E Rp[disp], Rs stswp.w E xchg E Rd, Rx, Ry 9.3.9.3 Multiple data Table 9-11. Mutiple data Mnemonics Operands / Syntax Rp{++}, Reglist16 ldm E {, R12={-1,0,1}} ldmts E Rp{++}, Reglist16 Reglist8 {, R12={- ...

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Table 9-12. System/Control (Continued) nop C pref E Rp[disp] sleep E Op8 sr{cond4 ssrf C bp sync E Op8 tlbr C tlbs C tlbw C AVR32 118 No operation Prefetch cache line Enter SLEEP mode. Conditionally set register ...

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Coprocessor interface Table 9-13. Coprocessor Interface Mnemonics Operands / Syntax CP#, CRd, CRx, cop E CRy CP#, CRd, Rp[disp] E CP#, CRd, --Rp ldc.d CP#, CRd, E Rb[Ri<<sa] ldc0.d E CRd, Rp[disp] E CP#, CRd, Rp[disp] E ...

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Table 9-13. Coprocessor Interface (Continued) CP#, {--}Rp, stcm.d E ReglistCPD8 CP#, {--}Rp, stcm.w E ReglistCPH8 CP#, {--}Rp, stcm.w E ReglistCPL8 9.3.12 Instructions to aid Java execution Table 9-14. Instructions to aid Java (Card) execution Mnemonics Operands / Syntax incjosp C ...

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Table 9-15. SIMD Operations (Continued) plsr.{b/h} E Rd, Rs, {sa} pmax.{ub/sh} E Rd, Rx, Ry pmin.{ub/sh} E Rd, Rx, Ry psad E Rd, Rx, Ry psub.{b/h} E Rd, Rx, Ry Rd, Rx:<part>, Ry:<part> psubadd.h E Rd, Rx:<part>, Ry:<part> psubaddh.sh E ...

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Base Instruction Set Description The following chapter describes the instructions in the base instruction set. AVR32 122 32000D–04/2011 ...

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ABS – Absolute Value Architecture revision: Architecture revision1 and higher. Description The absolute value of the contents to the register specified is written back to the register. If the initial value equals the maximum negative value (0x80000000), the result will ...

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ACALL – Application Call Architecture revision: Architecture revision1 and higher. Description The ACALL instruction performs an application function call. Operation: I. Syntax: I. Operands: I. Status Flags: Opcode Note: ACBA must be word aligned. Failing to align ACBA ...

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ACR – Add Carry to Register Architecture revision: Architecture revision1 and higher. Description Adds carry to the specified destination register Operands: I. Status Flags Opcode Example: 32000D–04/2011 Operation: Rd ← Syntax: acr Rd ...

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ADC – Add with Carry Architecture revision: Architecture revision1 and higher. Description Adds carry and the two registers specified and stores the result in destination register. Operation: I. Syntax: I. Operands: I. Status Flags: Opcode Example ...

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ADD– Add without Carry Architecture revision: Architecture revision1 and higher. Description Adds the two registers specified and stores the result in destination register. Format II allows shifting of the second operand. Operation: I. II. Syntax: I. II. Operands: I. II. ...

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ADD{cond4} – Conditional Add Architecture revision: Architecture revision 2 and higher. Description Performs an addition and stores the result in destination register. Operation: I. Syntax: I. Operands: I. Status Flags: Opcode AVR32 128 if ( cond4) ...

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ADDABS– Add Absolute Value Architecture revision: Architecture revision1 and higher. Description Adds Rx and the absolute value of Ry and stores the result in destination register. Useful for cal- culating the sum of absolute differences. Operation: I. Syntax: I. Operands: ...

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ADDHH.W– Add Halfwords into Word Architecture revision: Architecture revision1 and higher. Description Adds the two halfword registers specified and stores the result in the destination word-register. The halfword registers are selected as either the high or low part of the ...

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AND – Logical AND with optional logical shift Architecture revision: Architecture revision1 and higher. Description Performs a bitwise logical AND between the specified registers and stores the result in the desti- nation register. Operation: I. II. III. Syntax: I. II. ...

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AVR32 132 Format III sa5 32000D–04/2011 ...

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AND{cond4} – Conditional And Architecture revision: Architecture revision1 and higher. Architecture revision: Architecture revision 2 and higher. Description Performs a bitwise logical AND between the specified registers and stores the result in the desti- nation register. Operation: I. Syntax: I. ...

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ANDH, ANDL – Logical AND into high or low half of register Architecture revision: Architecture revision1 and higher. Description Performs a bitwise logical AND between the high or the low halfword in the specified register and a constant. The result ...

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Format III, IV COH imm16 AVR32 135 ...

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ANDN – Logical AND NOT Architecture revision: Architecture revision1 and higher. Description Performs a bitwise logical ANDNOT between the specified registers and stores the result in the destination register. Operation: I. Syntax: I. Operands: I. Status Flags Opcode(s ...

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ASR – Arithmetic Shift Right Architecture revision: Architecture revision1 and higher. Description Shifts all bits in a register to the right the amount of bits specified by the five least significant bits immediate while keeping the ...

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AVR32 138 Format Format II Bit[4:1] Format III ...

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BFEXTS – Bitfield extract and sign-extend Architecture revision: Architecture revision1 and higher. Description This instruction extracts and sign-extends the w5 bits in Rs starting at bit-offset bp5 to Rd. Operation: I. Syntax: I. Operands: I. Status Flags: Opcode ...

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BFEXTU – Bitfield extract and zero-extend Architecture revision: Architecture revision1 and higher. Description This instruction Operation: I. Syntax: I. Operands: I. Status Flags: Opcode Note: AVR32 140 extracts and zero-extends the w5 bits in Rs starting ...

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BFINS – Bitfield insert Architecture revision: Architecture revision1 and higher. Description This instruction inserts the lower w5 bits bit-offset bp5. Operation: I. Syntax: I. Operands: I. Status Flags: Opcode Note: 32000D–04/2011 ...

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BLD – Bit load from register to C and Z Architecture revision: Architecture revision1 and higher. Description Copy an arbitrary bit in a register to C and Z. Operation: I. Syntax: I. Operands: I. Status Flags Opcode ...

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BR{cond} – Branch if Condition Satisfied Architecture revision: Architecture revision1 and higher. Description Branch if the specified condition is satisfied. Operation: I. II. Syntax: I. II. Operands: I. II. Status Flags: Opcode 32000D–04/2011 if (cond3) PC ← PC ...

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AVR32 144 Format II disp21[20:1 disp21[15: d21 [16] 16 cond4 0 32000D–04/2011 ...

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BREAKPOINT – Software Debug Breakpoint Architecture revision: Architecture revision1 and higher. Description If the on chip debug system is enabled, this instruction traps a software breakpoint for debugging. The breakpoint instruc- tion will enter debug mode disabling all interrupts and ...

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BREV – Bit Reverse Architecture revision: Architecture revision1 and higher. Description Bit-reverse the contents in the register. Operation: I. Syntax: I. Operands: I. Status Flags: Opcode AVR32 146 Rd[31:0] ← Rd[0:31]; brev Rd d ∈{0, 1, …, 15} ...

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BST – Copy C to register bit Architecture revision: Architecture revision1 and higher. Description Copy the C-flag to an arbitrary bit in a register. Operation: I. Syntax: I. Operands: I. Status Flags: Opcode 32000D–04/2011 Rd[bp5] ← ...

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CACHE – Perform Cache control operation Architecture revision: Architecture revision1 and higher. Description Control cache operation. Operation: I. Syntax: I. Operands: I. Status Flags: AVR32 148 Issue a command to the cache cache Rp[disp], Op5 disp ∈ {-1024, -1023, ..., ...

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Opcode Note: This instruction can only be executed in a privileged mode. Execution from any other mode will trigger a Privilege Violation exception. 32000D–04/2011 Op5 ...

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CASTS.{H,B} – Typecast to Signed Word Architecture revision: Architecture revision1 and higher. Description Sign extends the halfword or byte that is specified to word size. The result is stored back to the specified register. Operation: I. II. Syntax: I. II. ...

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CASTU.{H,B} – Typecast to Unsigned Word Architecture revision: Architecture revision1 and higher. Description Zero extends the halfword or byte that is specified to word size. The result is stored back to the specified register. Operation: I. II. Syntax: I. II. ...

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CBR – Clear Bit in Register Architecture revision: Architecture revision1 and higher. Description Clears a bit in the specified register. All other bits are unaffected. Operation: I. Syntax: I. Operands: I. Status Flags: Opcode AVR32 152 Rd[bp5] ← ...

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CLZ – Count Leading Zeros Architecture revision: Architecture revision1 and higher. Description Counts the number of binary zero bits before the first binary one bit in a register value. The value returned from the operation can be used for doing ...

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COM – One’s Compliment Architecture revision: Architecture revision1 and higher. Description Perform a one’s complement of specified register. Operation: I. Syntax: I. Operands: I. Status Flags: Opcode AVR32 154 Rd ← ¬Rd; com Rd d ∈ {0, 1, ...

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COP – Coprocessor Operation Architecture revision: Architecture revision1 and higher. Description Addresses a coprocessor and performs the specified operation on the specified registers. Operation: I. Syntax: I. Operands: I. Status Flags: Opcode Example: 32000D–04/2011 CP#(CRd) ← CP#(CRx) ...

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CP.B – Compare Byte Architecture revision: Architecture revision1 and higher. Description Performs a compare between the lowermost bytes in the two operands specified. The operation is implemented by doing a subtraction without writeback of the difference. The operation sets the ...

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CP.H – Compare Halfword Architecture revision: Architecture revision1 and higher. Description Performs a compare between the lowermost halfwords in the two operands specified. The oper- ation is implemented by doing a subtraction without writeback of the difference. The operation sets ...

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CP.W – Compare Word Architecture revision: Architecture revision1 and higher. Description Performs a compare between the two operands specified. The operation is implemented by doing a subtraction without writeback of the difference. The operation sets the status flags according to ...

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Format III imm21[20: i21 [16] imm21[15:0 AVR32 159 ...

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CPC – Compare with Carry Architecture revision: Architecture revision1 and higher. Description Performs a compare between the two registers specified. The operation is executed by doing a subtraction with carry (as borrow) without writeback of the difference. The operation sets ...

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CSRF – Clear Status Register Flag Architecture revision: Architecture revision1 and higher. Description Clears the status register (SR) flag specified. Operation: I. Syntax: I. Operands: I. Status Flags: Opcode Note: Privileged if bp5 > 15, ie. upper half ...

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CSRFCZ – Copy Status Register Flag to C and Z Architecture revision: Architecture revision1 and higher. Description Copies the status register (SR) flag specified to C and Z. Operation: I. Syntax: I. Operands: I. Status Flags: Opcode Note: ...

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DIVS – Signed divide Architecture revision: Architecture revision1 and higher. Description Performs a signed divide between the two 32-bit register specified. The quotient is returned in Rd, the remainder in Rd+1. No exceptions are taken if dividing by 0. Result ...

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DIVU – Unsigned divide Architecture revision: Architecture revision1 and higher. Description Performs an unsigned divide between the two 32-bit register specified. The quotient is returned in Rd, the remainder in Rd+1. No exceptions are taken if dividing by 0. Result ...

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EOR – Logical Exclusive OR with optional logical shift Architecture revision: Architecture revision1 and higher. Description Performs a bitwise logical Exclusive-OR between the specified registers and stores the result in the destination register. Operation: I. II. III. Syntax: I. II. ...

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AVR32 166 Format III sa5 32000D–04/2011 ...

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EOR{cond4} – Conditional Logical EOR Architecture revision: Architecture revision 2 and higher. Description Performs a bitwise logical Exclusive-OR between the specified registers and stores the result in the destination register. Operation: I. Syntax: I. Operands: I. Status Flags: Opcode: 31 ...

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EORH, EORL – Logical EOR into high or low half of register Architecture revision: Architecture revision1 and higher. Description Performs a bitwise logical Exclusive-OR between the high or low halfword in the specified regis- ter and a constant. The result ...

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FRS – Flush Return Stack Architecture revision: Architecture revision1 and higher. Description Special instruction to invalidate the return address stack. This instruction is used when the user writes code that conflicts with the semantics required by the return address stack. ...

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ICALL – Indirect Call to Subroutine Architecture revision: Architecture revision1 and higher. Description Call to a subroutine pointed to by the pointer residing in Rp. Operation: I. Syntax: I. Operands: I. Status Flags: Opcode AVR32 170 LR ← ...

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INCJOSP – Increment Java Operand Stack Pointer Architecture revision: Architecture revision1 and higher. Description Increment the system register "Java Operand Stack Pointer" with value. Operation: I. Syntax: I. Operands: I. Status Flags: Opcode 32000D–04/2011 if ( JOSP[3:0] + ...

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Note: When trapped, this instruction will destroy R12 the programmer’s responsibility to keep the R12value if needed. AVR32 172 32000D–04/2011 ...

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LD.D – Load Doubleword Architecture revision: Architecture revision1 and higher. Description Reads the doubleword memory location specified. Operation: I. II. III. IV. V. Syntax: I. II. III. IV. V. Operands: I-V. IV. V. Status Flags: Opcode 32000D–04/2011 Rd+1:Rd ...

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Note: Format I and II Rp, the result is UNDEFINED. AVR32 174 Format II Format III ...

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LD.SB – Load Sign-extended Byte Architecture revision: Architecture revision1 and higher. Description Reads the byte memory location specified and sign-extends it. Operation: I. II. Syntax: I. II. Operands: I. II. Status Flags: Opcode ...

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LD.SB{cond4} – Conditionally Load Sign-extended Byte Architecture revision: Architecture revision 2 and higher. Description Reads the byte memory location specified and sign-extends it if the given condition is satisfied. Operation: I. Syntax: I. Operands: I. Status Flags: Opcode ...

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LD.UB – Load Zero-extended Byte Architecture revision: Architecture revision1 and higher. Description Reads the byte memory location specified and zero-extends it. Operation: I. II. III. IV. V. Syntax: I. II. III. IV. V. Operands: I-V. III. IV. V. Status Flags: ...

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Note: Format I and II Rp, the result is UNDEFINED. AVR32 178 Format II Format III ...

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LD.UB{cond4} – Conditionally Load Zero-extended Byte Architecture revision: Architecture revision 2 and higher. Description Reads the byte memory location specified and zero-extends it if the given condition is satisfied. Operation: I. Syntax: I. Operands: I. Status Flags: Opcode ...

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LD.SH – Load Sign-extended Halfword Architecture revision: Architecture revision1 and higher. Description Reads the halfword memory location specified and sign-extends it. Operation: I. II. III. IV. V. Syntax: I. II. III. IV. V. Operands: I-V. III. IV. V. Status Flags: ...

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Note: Format I and II Rp, the result is UNDEFINED. 32000D–04/2011 Format II Format III ...

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LD.SH{cond4} – Conditionally Load Sign-extended Halfword Architecture revision: Architecture revision 2 and higher. Description Reads the halfword memory location specified and sign-extends it if the given condition is satis- fied. Operation: I. Syntax: I. Operands: I. Status Flags: Opcode: 31 ...

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LD.UH – Load Zero-extended Halfword Architecture revision: Architecture revision1 and higher. Description Reads the halfword memory location specified and zero-extends it. Operation: I. II. III. IV. V. Syntax: I. II. III. IV. V. Operands: I-V. III. IV. V. Status Flags: ...

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Note: Format I and II Rp, the result is UNDEFINED. AVR32 184 Format II Format III ...

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LD.UH{cond4} – Conditionally Load Zero-extended Halfword Architecture revision: Architecture revision 2 and higher. Description Reads the halfword memory location specified and zero-extends it if the given condition is satis- fied. Operation: I. Syntax: I. Operands: I. Status Flags: Opcode: 31 ...

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LD.W – Load Word Architecture revision: Architecture revision1 and higher. Description Format Reads the word memory location specified. Format VI: This instruction extracts a specified byte from Ri. This value is zero-extended, shifted left two positions and ...

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Status Flags: Opcode Note: Format I and II Rp, the result is UNDEFINED. 32000D–04/2011 Q: Not affected. V: Not affected. ...

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AVR32 188 32000D–04/2011 ...

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LD.W{cond4} – Conditionally Load Word Architecture revision: Architecture revision 2 and higher. Description Reads the word memory location specified if the given condition is satisfied. Operation: I. Syntax: I. Operands: I. Status Flags: Opcode 32000D–04/2011 if (cond4) ...

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LDC.{D,W} – Load Coprocessor Architecture revision: Architecture revision1 and higher. Description Reads the memory location specified into the addressed coprocessor. Operation: I. II. III. IV. V. VI. Syntax: I. II. III. IV. V. VI. Operands: I-VI. I-II, IV-V.p ∈ {0, ...

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Example: 32000D–04/2011 Format CRd[3:1] Format II: ...

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LDC0.{D,W} – Load Coprocessor 0 Architecture revision: Architecture revision1 and higher. Description Reads the memory location specified into coprocessor 0. Operation: I. II. Syntax: I. II. Operands: I,II I. II. I, II. Status Flags: Opcode disp[11:8] 31 ...

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LDCM.{D,W} – Load Coprocessor Multiple Registers Architecture revision: Architecture revision1 and higher. Description Reads the memory locations specified into the addressed coprocessor. The pointer register can optionally be updated after the operation. Operation: I. II. III. Syntax: I. II. III. ...

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Status Flags: Opcode CP CP CP# Example: Note: Emtpy ReglistCPL8/ReglistCPL8/ReglistCPD8 gives UNDEFINED result. AVR32 194 Q: Not affected. V: Not affected. N: Not affected. Z: Not affected. C: Not affected. Format ...

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LDDPC – Load PC-relative with Displacement Architecture revision: Architecture revision1 and higher. Description Performs a PC relative load of a register Operation: I. Syntax: I. Operands: I. Status Flags: Opcode 32000D–04/2011 Rd ← *( (PC && 0xFFFF_FFFC) + ...

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LDDSP – Load SP-relative with Displacement Architecture revision: Architecture revision1 and higher. Description Reads the value of a memory location referred to by the stack pointer register and a displace- ment. Operation: I. Syntax: I. Operands: I. Status Flags: Opcode: ...

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LDINS.{B,H} – Load and Insert Byte or Halfword into register Architecture revision: Architecture revision1 and higher. Description This instruction loads a byte or a halfword from memory and inserts it into the addressed byte or halfword position in Rd. The ...

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Opcode AVR32 198 Format part Format II part 24 ...

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LDM – Load Multiple Registers Architecture revision: Architecture revision1 and higher. Description Loads the consecutive words pointed into the registers specified in the instruction. The PC can be loaded, resulting in a jump to the loaded target ...

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Syntax: I. Operands: I. Status Flags: Opcode R15 R14 R13 R12 R11 R10 R9 Note: Emtpy Reglist16 gives UNDEFINED result Reglist16 and pointer is written back the result is UNDEFINED. The R bit ...

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