AT32UC3C2256C Atmel Corporation, AT32UC3C2256C Datasheet - Page 206

• Manufacturer Part Number: AT32UC3C2256C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C2256C

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 45
• Ext Interrupts: 64
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 13
• Input Capture Channels: 6
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

206
AVR32
LSR – Logical Shift Right
Architecture revision:
Architecture revision1 and higher.
Description
Shifts all bits in a register the amount specified to the right. The shift amount may be specified by
a register or an immediate. Zeros are shifted into the MSB.
Operation:
I.
II.
III.
Syntax:
I.
II.
III.
Operands:
I.
II.
III.
Status Flags:
Rd ← LSR(Rx, Ry[4:0]);
Rd ← LSR(Rd, sa5);
Rd ← LSR(Rs, sa5);
lsr
lsr
lsr
{d, x, y} ∈ {0, 1, …, 15}
d ∈ {0, 1, …, 15}
sa ∈ {0, 1, …, 31}
{d,s} ∈ {0, 1, …, 15}
sa ∈ {0, 1, …, 31}
Format I: Shamt = Ry[4:0], Op = Rx
Format II: Shamt = sa5, Op = Rd
Format III: Shamt = sa5, Op = Rs
Q:
V:
N:
Z:
C:
Not affected
Not affected
N ← RES[31]
Z ← (RES[31:0] == 0)
if Shamt != 0
else
Rd, Rx, Ry
Rd, sa
Rd, Rs, sa
C ← Op[Shamt-1]
C ← 0
32000D–04/2011