AT32UC3C2256C Atmel Corporation, AT32UC3C2256C Datasheet - Page 7

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AT32UC3C2256C

Manufacturer Part Number
AT32UC3C2256C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of AT32UC3C2256C

Flash (kbytes)
256 Kbytes
Pin Count
64
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
45
Ext Interrupts
64
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
5
Twi (i2c)
2
Uart
4
Can
2
Lin
4
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
2
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
68
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
13
Input Capture Channels
6
Pwm Channels
14
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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2.4
2.4.1
2.4.2
2.4.3
2.4.4
32000D–04/2011
Processor States
Normal RISC State
Debug State
Java State
Secure State
The AVR32 processor supports several different execution contexts as shown in
page
Table 2-3.
Mode changes can be made under software control, or can be caused by external interrupts or
exception processing. A mode can be interrupted by a higher priority mode, but never by one
with lower priority. Nested exceptions can be supported with a minimal software overhead.
When running an operating system on the AVR32, user processes will typically execute in the
application mode. The programs executed in this mode are restricted from executing certain
instructions. Furthermore, most system registers together with the upper halfword of the status
register cannot be accessed. Protected memory areas are also not available. All other operating
modes are privileged and are collectively called System Modes. They have full access to all priv-
ileged and unprivileged resources. After a reset, the processor will be in supervisor mode.
The AVR32 can be set in a debug state, which allows implementation of software monitor rou-
tines that can read out and alter system information for use during application development. This
implies that all system and application registers, including the status registers and program
counters, are accessible in debug state. The privileged instructions are also available.
All interrupt levels are by default disabled when debug state is entered, but they can individually
be switched on by the monitor routine by clearing the respective mask bit in the status register.
Debug state can be entered as described in the Technical Reference Manual.
Debug state is exited by the retd instruction.
Some versions of the AVR32 processor core comes with a Java Extension Module (JEM). The
processor can be set in a Java State where normal RISC operations are suspended. The Java
state is described in chapter 3.
The secure state added in the AVR32 Architecture revision 3 allows executing secure or trusted
software in alongside nonsecure or untrusted software on the same processor. Hardware mech-
Priority
1
2
3
4
5
6
N/A
N/A
7.
Mode
Non Maskable Interrupt
Exception
Interrupt 3
Interrupt 2
Interrupt 1
Interrupt 0
Supervisor
Application
Overview of execution modes, their priorities and privilege levels.
Security
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Unprivileged
Description
Non Maskable high priority interrupt mode
Execute exceptions
General purpose interrupt mode
General purpose interrupt mode
General purpose interrupt mode
General purpose interrupt mode
Runs supervisor calls
Normal program execution mode
Table 2-3 on
AVR32
7

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