AT32UC3C2256C Atmel Corporation, AT32UC3C2256C Datasheet - Page 209

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AT32UC3C2256C

Manufacturer Part Number
AT32UC3C2256C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of AT32UC3C2256C

Flash (kbytes)
256 Kbytes
Pin Count
64
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
45
Ext Interrupts
64
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
5
Twi (i2c)
2
Uart
4
Can
2
Lin
4
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
2
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
68
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
13
Input Capture Channels
6
Pwm Channels
14
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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32000D–04/2011
MACHH.D – Multiply Halfwords and Accumulate in Doubleword
Architecture revision:
Architecture revision1 and higher.
Description
Multiplies the two halfword registers specified and adds the result to the specified doubleword-
register. Only the 48 highest of the 64 possible bits in the doubleword accumulator are used. The
16 lowest bits are cleared. The halfword registers are selected as either the high or low part of
the operand registers.
Operation:
I.
Syntax:
I.
Operands:
I.
Status Flags:
Opcode:
Example:
31
1
15
0
If (Rx-part == t) then operand1 = SE(Rx[31:16]) else operand1 = SE(Rx[15:0]);
If (Ry-part == t) then operand2 = SE(Ry[31:16]) else operand2 = SE(Ry[15:0]);
(Rd+1:Rd)[63:16] ← (operand1 × operand2)[31:0] + (Rd+1:Rd)[63:16];
Rd[15:0] ← 0;
machh.d Rd, Rx:<part>, Ry:<part>
d ∈ {0, 2, 4, …, 14}
{x, y} ∈ {0, 1, …, 15}
part ∈ {t,b}
Q:
V:
N:
Z:
C:
machh.d R10, R2:t, R3:b will perform
(R11 : R10)[63:16] ← ( SE(R2[31:16]) × SE(R3[15:0]) ) + (R11 : R10)[63:16]
R10[15:0] ← 0
1
0
29
1
0
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
28
12
0
11
0
Rx
1
25
0
8
24
0
1
7
0
1
6
0
0
5
X
0
4
Y
20
0
3
19
Ry
Rd
AVR32
0
16
209

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