AT32UC3C2256C Atmel Corporation, AT32UC3C2256C Datasheet - Page 73

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AT32UC3C2256C

Manufacturer Part Number
AT32UC3C2256C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of AT32UC3C2256C

Flash (kbytes)
256 Kbytes
Pin Count
64
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
45
Ext Interrupts
64
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
5
Twi (i2c)
2
Uart
4
Can
2
Lin
4
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
2
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
68
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
13
Input Capture Channels
6
Pwm Channels
14
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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8.3.1.11
8.3.1.12
32000D–04/2011
INT0 Exception
Instruction Address Exception
The INT0 exception is generated when the INT0 input line to the core is asserted. The INT0
exception can be masked by the SR[GM] bit, and the SR[I0M] bit. Hardware automatically sets
the SR[I0M] bit when accepting an INT0 exception, inhibiting new INT0 requests when process-
ing an INT0 request.
The INT0 Exception handler address is calculated by adding EVBA to an interrupt vector offset
specified by an interrupt controller outside the core. The interrupt controller is responsible for
providing the correct offset.
Since the INT0 exception is unrelated to the instruction stream, the instructions in the pipeline
are allowed to complete. After finishing the INT0 exception routine, execution should continue at
the instruction following the last completed instruction in the instruction stream.
The Instruction Address Error exception is generated if the generated instruction memory
address has an illegal alignment.
*(--SP
*(--SP
*(--SP
*(--SP
*(--SP
*(--SP
*(--SP
*(--SP
SR[R] = 0;
SR[J] = 0;
SR[M2:M0] = B’010;
SR[I0M] = 1;
PC = EVBA + INTERRUPT_VECTOR_OFFSET;
*(--SP
*(--SP
TLBEAR = FAILING_VIRTUAL_ADDRESS;
TLBEHI[VPN] = FAILING_PAGE_NUMBER;
SR[R] = 0;
SR[J] = 0;
SR[M2:M0] = B’110;
SR[EM] = 1;
SR[GM] = 1;
PC = EVBA + 0x14;
SYS
SYS
SYS
SYS
SYS
SYS
SYS
SYS
SYS
SYS
) = R8;
) = R9;
) = R10;
) = R11;
) = R12;
) = LR;
) = PC of first noncompleted instruction;
) = SR;
) = PC;
) = SR;
AVR32
73

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