AT32UC3C2256C Atmel Corporation, AT32UC3C2256C Datasheet - Page 66

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AT32UC3C2256C

Manufacturer Part Number
AT32UC3C2256C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of AT32UC3C2256C

Flash (kbytes)
256 Kbytes
Pin Count
64
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
45
Ext Interrupts
64
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
5
Twi (i2c)
2
Uart
4
Can
2
Lin
4
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
2
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
68
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
13
Input Capture Channels
6
Pwm Channels
14
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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8.3
Entry points for events
Several different event handler entry points exists. For AVR32A, the reset routine is placed at
address 0x8000_0000. This places the reset address in the flash memory area. For AVR32B,
the reset routine entry address is always fixed to 0xA000_0000. This address resides in
unmapped, uncached space in order to ensure well-defined resets.
TLB miss exceptions and scall have a dedicated space relative to EVBA where their event han-
dler can be placed. This speeds up execution by removing the need for a jump instruction placed
at the program address jumped to by the event hardware. All other exceptions have a dedicated
event routine entry point located relative to EVBA. The handler routine address identifies the
exception source directly.
All external interrupt requests have entry points located at an offset relative to EVBA. This
autovector offset is specified by an external Interrupt Controller. The programmer must make
sure that none of the autovector offsets interfere with the placement of other code. The reach of
the autovector offset is IMPLEMENTATION DEFINED.
Special considerations should be made when loading EVBA with a pointer. Due to security con-
siderations, the event handlers should be located in the privileged address space, or in a
privileged memory protection region. In a system with MPU, the event routines could be placed
in a cacheable protection region. In a segmented AVR32B system, some segments of the virtual
memory space may be better suited than others for holding event handlers. This is due to differ-
ences in translateability and cacheability between segments. A cacheable, non-translated
segment may offer the best performance for event handlers, as this will eliminate any TLB
misses and speed up instruction fetch. The user may also consider to lock the event handlers in
the instruction cache.
If several events occur on the same instruction, they are handled in a prioritized way. The priority
ordering is presented in Table 8-1. If events occur on several instructions at different locations in
the pipeline, the events on the oldest instruction are always handled before any events on any
younger instruction, even if the younger instruction has events of higher priority than the oldest
instruction. An instruction B is younger than an instruction A if it was sent down the pipeline later
than A.
The addresses and priority of simultaneous events are shown in
Table 8-1 on page 67
AVR32
66
32000D–04/2011

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