AT32UC3C2256C Atmel Corporation, AT32UC3C2256C Datasheet - Page 115

• Manufacturer Part Number: AT32UC3C2256C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C2256C

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 45
• Ext Interrupts: 64
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 13
• Input Capture Channels: 6
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Table 9-10.
32000D–04/2011
ld.sh
ld.sh{cond4}
ld.w
ld.w{cond4}
ld.d
ldins.b
ldins.h
ldswp.sh
ldswp.uh
ldswp.w
lddpc
lddsp
Load/Store Operations (Continued)
C
C
C
E
E
E
C
C
C
E
E
E
E
C
C
C
E
E
E
E
E
E
E
C
C
Rd, Rp++
Rd, --Rp
Rd, Rp[disp]
Rd, Rp[disp]
Rd, Rb[Ri<<sa]
Rd, Rp[disp]
Rd, Rp++
Rd, --Rp
Rd, Rp[disp]
Rd, Rp[disp]
Rd, Rb[Ri<<sa]
Rd, Rb[Ri:<part> <<
2]
Rd, Rp[disp]
Rd, Rp++
Rd, --Rp
Rd, Rp
Rd, Rp[disp]
Rd, Rb[Ri<<sa]
Rd:<part>, Rp[disp]
Rd:<part>, Rp[disp]
Rd, Rp[disp]
Rd, PC[disp]
Rd, SP[disp]
Load signed halfword with post-
increment.
Load signed halfword with pre-decrement.
Load signed halfword with displacement.
Indexed Load signed halfword.
Load signed halfword with displacement if
condition satisfied.
Load word with post-increment.
Load word with pre-decrement.
Load word with displacement.
Indexed Load word.
Load word with extracted index into Rd.
Load word with displacement if condition
satisfied.
Load doubleword with post-increment.
Load doubleword with pre-decrement.
Load doubleword.
Load double with displacement.
Indexed Load double.
Load byte with displacement and insert at
specified byte location in Rd.
Load halfword with displacement and
insert at specified halfword location in Rd.
Load halfword with displacement, swap
bytes and sign-extend
Load halfword with displacement, swap
bytes and zero-extend
Load word with displacement and swap
bytes.
Load with displacement from PC.
Load with displacement from SP.
Rd ← SE(*(Rp++))
Rd ← SE(*(--Rp))
Rd ← SE(*(Rp+(ZE(disp3)<<1)))
Rd ← SE(*(Rp+(SE(disp16))))
Rd ← SE(*(Rb+(Ri << sa2)))
if {cond4}
Rd ← SE(*(Rp+ZE(disp9<<1)))
Rd ← *(Rp++)
Rd ← *(--Rp)
Rd ← *(Rp+(ZE(disp5)<<2))
Rd ← *(Rp+(SE(disp16)))
Rd ← *(Rb+(Ri << sa2))
Rd ← *(Rb+(Ri:<part> << 2))
if {cond4}
Rd ← *(Rp+ZE(disp9<<2))
Rd+1:Rd ← (*(Rp++))
Rd+1:Rd ← (*(--Rp))
Rd+1:Rd ← *(Rp)
Rd+1:Rd ← *(Rp+SE(disp16))
Rd+1:Rd ← *(Rb+(Ri << sa2))
Rd:<part>← *(Rp+(SE(disp12)))
Rd:<part> ←
*(Rp+(SE(disp12)<<1))
Temp ← *(Rp+(SE(disp12) << 1)
Rd ← SE(Temp[7:0], Temp[15:8])
Temp ← *(Rp+(SE(disp12) << 1)
Rd ← ZE(Temp[7:0], Temp[15:8])
Temp ← *(Rp+(SE(disp12) << 2)
Rd[31:24] ← Temp[7:0],
Rd[23:16] ← Temp[15:8],
Rd[15:8] ← Temp[23:16],
Rd[7:0] ← Temp[31:24]
Rd ← *((PC && 0xFFFF_FFFC)
+(ZE(disp7)<<2))
Rd ← *((SP && 0xFFFF_FFFC)
+(ZE(disp7)<<2))
AVR32
1
1
1
1
1
2
1
1
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
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