AT32UC3C2256C Atmel Corporation, AT32UC3C2256C Datasheet - Page 346

• Manufacturer Part Number: AT32UC3C2256C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C2256C

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 45
• Ext Interrupts: 64
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 13
• Input Capture Channels: 6
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

346
AVR32
STC0.{D,W} – Store Coprocessor 0 Register
Architecture revision:
Architecture revision1 and higher.
Description
Stores the coprocessor 0 source register value to the location specified by the addressing mode.
Operation:
I.
II.
Syntax:
I.
II.
Operands:
I-II.
I.
II.
I, IV.
Status Flags:
Opcode:
Example:
15
15
31
31
1
1
disp[11:8]
disp[11:8]
*(Rp + (ZE(disp12) << 2)) ← CP#(CRd+1:CRd);
*(Rp + (ZE(disp12) << 2)) ← CP#(CRd);
stc0.d Rp[disp], CRs
stc0.w Rp[disp], CRs
p ∈ {0, 1, …, 15}
s ∈ {0, 2, …, 14}
s ∈ {0, 1, …, 15}
disp ∈ {0, 4, …, 16380}
Q:
V:
N:
Z:
C:
Format I:
Format II:
stc0.d R2[0], CR0
1
1
29
29
1
1
Not affected
Not affected
Not affected
Not affected
Not affected
12
12
28
28
1
1
11
11
CRs[3:1]
0
0
CRs
1
1
25
1
25
0
8
8
24
1
24
1
0
7
7
1
1
0
0
1
1
20
0
20
0
disp[7:0]
disp[7:0]
19
19
Rp
Rp
32000D–04/2011
0
0
16
16